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7028L20PFG PDF预览

7028L20PFG

更新时间: 2024-10-30 00:58:15
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
18页 179K
描述
HIGH-SPEED 64K x 16 DUAL-PORT STATIC RAM

7028L20PFG 技术参数

生命周期:Active包装说明:QFP,
Reach Compliance Code:compliantHTS代码:8542.32.00.41
风险等级:5.77Is Samacsys:N
最长访问时间:20 nsJESD-30 代码:S-PQFP-G100
内存密度:1048576 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:16功能数量:1
端子数量:100字数:65536 words
字数代码:64000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:64KX16封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装形状:SQUARE
封装形式:FLATPACK并行/串行:PARALLEL
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子位置:QUAD
Base Number Matches:1

7028L20PFG 数据手册

 浏览型号7028L20PFG的Datasheet PDF文件第2页浏览型号7028L20PFG的Datasheet PDF文件第3页浏览型号7028L20PFG的Datasheet PDF文件第4页浏览型号7028L20PFG的Datasheet PDF文件第5页浏览型号7028L20PFG的Datasheet PDF文件第6页浏览型号7028L20PFG的Datasheet PDF文件第7页 
HIGH-SPEED  
64K x 16 DUAL-PORT  
STATIC RAM  
IDT7028L  
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018  
Features  
True Dual-Ported memory cells which allow simultaneous  
M/S = VIH for BUSY output flag on Master,  
M/S = VIL for BUSY input on Slave  
Interrupt Flag  
On-chip port arbitration logic  
Full on-chip hardware support of semaphore signaling  
between ports  
Fully asynchronous operation from either port  
Separate upper-byte and lower-byte controls for multi-  
plexed bus and bus matching compatibility  
TTL-compatible, single 5V ( 10%) power supply  
Available in a 100-pin TQFP  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
Green parts available, see ordering information  
reads of the same memory location  
High-speed access  
– Commercial: 15/20ns (max.)  
– Industrial: 20ns (max.)  
Low-power operation  
– IDT7028L  
Active: 1W (typ.)  
Standby: 1mW (typ.)  
Dual chip enables allow for depth expansion without  
external logic  
IDT7028 easily expands data bus width to 32 bits or  
more using the Master/Slave select when cascading more  
than one device  
Functional Block Diagram  
R/  
W
L
R/W  
UB  
R
UB  
L
R
CE0L  
CE0R  
CE1L  
CE1R  
OE  
R
OE  
L
L
LBR  
LB  
I/O8-15L  
I/O8-15R  
I/O0-7R  
I/O  
Control  
I/O  
Control  
0-7L  
I/O  
(1,2)  
(1,2)  
BUSY  
R
BUSY  
L
64Kx16  
MEMORY  
ARRAY  
7028  
15L  
A
15R  
0R  
A
Address  
Decoder  
Address  
Decoder  
A
0L  
A
16  
16  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE0R  
CE0L  
CE1L  
OEL  
CE1R  
OER  
R/W  
L
R/WR  
SEM  
L
L
SEM  
R
(2)  
(2)  
INTR  
INT  
M/S(2)  
NOTES:  
1. BUSY is an input as a Slave (M/S = VIL) and an output when it is a Master (M/S = VIH).  
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).  
4836 drw 01  
JUNE 2018  
1
DSC-4836/5  
©2015 Integrated Device Technology, Inc.  

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