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7024L35PF9 PDF预览

7024L35PF9

更新时间: 2024-12-01 07:59:03
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
21页 190K
描述
Dual-Port SRAM, 4KX16, 35ns, CMOS, PQFP100, TQFP-100

7024L35PF9 数据手册

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HIGH-SPEED  
IDT7024S/L  
4K x 16 DUAL-PORT  
STATIC RAM  
IDT7024 easily expands data bus width to 32 bits or more  
using the Master/Slave select when cascading more than  
one device  
M/S = H for BUSY output flag on Master  
M/S = L for BUSY input on Slave  
Interrupt Flag  
On-chip port arbitration logic  
Full on-chip hardware support of semaphore signaling  
between ports  
Fully asynchronous operation from either port  
Battery backup operation2V data retention  
TTL-compatible, single 5V (±10%) power supply  
Available in 84-pin PGA, Flatpack, PLCC, and 100-pin Thin  
Quad Flatpack  
Features  
True Dual-Ported memory cells which allow simultaneous  
reads of the same memory location  
High-speed access  
Military:20/25/35/55/70ns(max.)  
Industrial:55ns (max.)  
– Commercial:15/17/20/25/35/55ns(max.)  
Low-power operation  
IDT7024S  
Active:750mW(typ.)  
Standby: 5mW (typ.)  
IDT7024L  
Active:750mW(typ.)  
Standby: 1mW (typ.)  
Separate upper-byte and lower-byte control for multiplexed  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
bus compatibility  
FunctionalBlockDiagram  
R/WL  
UBL  
R/WR  
UBR  
LBL  
CEL  
OEL  
R
CER  
OER  
LB  
I/O8L-I/O15L  
I/O8R-I/O15R  
I/O  
I/O  
Control  
Control  
I/O0L-I/O7L  
0R  
I/O -I/O  
7R  
(1,2)  
BUSYL  
(1,2)  
BUSYR  
A11R  
A0R  
A11L  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A0L  
12  
12  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CER  
OER  
CEL  
OE  
L
WR  
R/  
R/WL  
SEMR  
(2)  
SEML  
(2)  
M/S  
INTR  
2740 drw 01  
INTL  
NOTES:  
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.  
2. BUSY outputs and INT outputs are non-tri-stated push-pull.  
APRIL 2000  
1
DSC 2740/10  
©2000IntegratedDeviceTechnology,Inc.  

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