Datasheet > 7019L15PFGI

7019L15PFGI

更新时间： 2024-11-17 01:10:15

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
17页	160K
描述
HIGH-SPEED 128K x 9 DUAL-PORT STATIC RAM

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中文翻译

获取价格

数据手册

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7019L15PFGI 数据手册

HIGH-SPEED

128K x 9 DUAL-PORT

STATIC RAM

IDT7019L

Features

◆

than one device

True Dual-Ported memory cells which allow simultaneous

◆

M/S = VIH for BUSY output flag on Master,

M/S = VIL for BUSY input on Slave

Interrupt Flag

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

TTL-compatible, single 5V (±10%) power supply

Available in a 100-pin TQFP

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

reads of the same memory location

High-speed access

◆

– Commercial: 15/20ns (max.)

– Industrial: 20ns (max.)

Low-power operation

◆

– IDT7019L

◆

Active: 1W (typ.)

Standby: 1mW (typ.)

Dual chip enables allow for depth expansion without

◆

external logic

◆

IDT7019 easily expands data bus width to 18 bits or

◆

Green parts available, see ordering information

more using the Master/Slave select when cascading more

FunctionalBlockDiagram

R/W

CE0L

CE1L

CE0R

CE1R

OE_L

OE_R

I/O

Control

I/O

Control

I/O0-8L

I/O_0-8R

(1,2)

BUSY_L

(1,2)

BUSY_R

128Kx9

MEMORY

ARRAY

7019

16L

16R

Address

Decoder

Address

Decoder

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CE_0L

CE_0R

R/W

SEM

INT

(2)

INTL

M/S⁽¹⁾

4840 drw 01

NOTES:

1. BUSY is an input as a Slave (M/S = VIL) and an output when it is a Master (M/S = VIH).

2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).

SEPTEMBER 2013

DSC-4840/5

12 3 4 5 6 7...17

中文翻译

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