Datasheet > 7019L15PFI

7019L15PFI

更新时间： 2024-11-16 21:03:23

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
17页	143K
描述
SRAM

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中文翻译

获取价格

技术参数
数据手册

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7019L15PFI 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	,	Reach Compliance Code：	not_compliant
风险等级：	5.92	JESD-609代码：	e0
湿度敏感等级：	3	端子面层：	Tin/Lead (Sn85Pb15)
Base Number Matches：	1

7019L15PFI 数据手册

HIGH-SPEED

IDT7019L

128K x 9 DUAL-PORT

STATIC RAM

Features

◆

M/S = VIH for BUSY output flag on Master,

M/S = VIL for BUSY input on Slave

Interrupt Flag

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

◆

On-chip port arbitration logic

– Commercial:15/20ns (max.)

Low-power operation

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

TTL-compatible, single 5V (±10%) power supply

Available in a 100-pin TQFP

– IDT7019L

◆

Active:1W(typ.)

Standby: 1mW (typ.)

◆

Dual chip enables allow for depth expansion without

external logic

IDT7019 easily expands data bus width to 18 bits or

more using the Master/Slave select when cascading more

than one device

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

FunctionalBlockDiagram

R/WL

CE0L

CE1L

R/WR

CE0R

CE1R

OE_L

OE_R

I/O

Control

I/O

Control

I/O0-8L

I/O_0-8R

(1,2)

BUSY_L

(1,2)

BUSY_R

128Kx9

MEMORY

ARRAY

7019

A16L

A16R

A0R

Address

Decoder

Address

Decoder

A0L

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CE0L

CE_0R

OEL

OER

R/W

SEM_L

(2)

INTL

SEMR

(2)

INT

M/S⁽¹⁾

4840 drw 01

NOTES:

1. BUSY is an input as a Slave (M/S = V^IL) and an output when it is a Master (M/S = VIH).

2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).

JANUARY 2001

DSC-4840/2

12 3 4 5 6 7...17

中文翻译

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