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662M-03 PDF预览

662M-03

更新时间: 2024-11-08 19:47:55
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
7页 183K
描述
PLL Based Clock Driver, 87931 Series, 1 True Output(s), 0 Inverted Output(s), PDSO8, 0.150 INCH, SOIC-8

662M-03 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:0.150 INCH, SOIC-8
针数:8Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.2
系列:87931输入调节:STANDARD
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
长度:4.9 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:8
实输出次数:1最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE认证状态:Not Qualified
座面最大高度:1.75 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:3.9 mmBase Number Matches:1

662M-03 数据手册

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DATASHEET  
HDTV AUDIO/VIDEO CLOCK SOURCE  
ICS662-03  
Description  
Features  
The ICS662-03 provides synchronous clock generation for  
audio sampling clock rates derived from an HDTV stream.  
The device uses the latest PLL technology to provide  
superior phase noise and long term jitter performance. The  
device also supports a 27 MHz output clock for video  
MPEG applications from an HDTV reference clock.  
Packaged in 8-pin SOIC  
Available in Pb (lead) free package  
HDTV clock input  
Low phase noise  
Exact (0 ppm) multiplication ratios  
Support for 256 and 384 times sampling rate  
Supports 27 MHz output for video (MPEG)  
NOTE: EOL for non-green parts to occur on 5/13/10  
per PDN U-09-01  
Please contact IDT if you have a requirement for an input  
and output frequency not included here.  
Block Diagram  
VDD  
Control  
SEL3:0  
Circuitry  
PLL  
Clock  
Synthesis  
CLK  
REF_IN  
GND  
IDT™ / ICS™ HDTV AUDIO/VIDEO CLOCK SOURCE  
1
ICS662-03  
REV F 110409  

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