Datasheet > 662M-03T

662M-03T

更新时间： 2024-01-18 04:47:37

品牌	Logo	应用领域
艾迪悌 - IDT		驱动光电二极管逻辑集成电路
页数	文件大小	规格书
7页	170K
描述
PLL Based Clock Driver, 662 Series, 1 True Output(s), 0 Inverted Output(s), PDSO8, 0.150 INCH, SOIC-8

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662M-03T 技术参数

DATASHEET

HDTV AUDIO/VIDEO CLOCK SOURCE

ICS662-03

Description

Features

The ICS662-03 provides synchronous clock generation for

audio sampling clock rates derived from an HDTV stream.

The device uses the latest PLL technology to provide

superior phase noise and long term jitter performance. The

device also supports a 27 MHz output clock for video

MPEG applications from an HDTV reference clock.

• Packaged in 8-pin SOIC

• Available in Pb (lead) free package

• HDTV clock input

• Low phase noise

• Exact (0 ppm) multiplication ratios

• Support for 256 and 384 times sampling rate

• Supports 27 MHz output for video (MPEG)

Please contact ICS if you have a requirement for an input

and output frequency not included here.

Block Diagram

VDD

Control

SEL3:0

Circuitry

PLL

Clock

CLK

Synthesis

REF_IN

GND

IDT™ / ICS™ HDTV AUDIO/VIDEO CLOCK SOURCE

ICS662-03

REV E 101807

12 3 4 5 6 7

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