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621S PDF预览

621S

更新时间: 2024-10-29 14:57:47
品牌 Logo 应用领域
瑞萨 - RENESAS /
页数 文件大小 规格书
13页 407K
描述
Low Skew 1 to 4 Clock Buffer

621S 数据手册

 浏览型号621S的Datasheet PDF文件第3页浏览型号621S的Datasheet PDF文件第4页浏览型号621S的Datasheet PDF文件第5页浏览型号621S的Datasheet PDF文件第7页浏览型号621S的Datasheet PDF文件第8页浏览型号621S的Datasheet PDF文件第9页 
Phase Noise Plots  
Figure 2. 621S Output Phase Noise 77fs  
(12kHz to 20MHz)  
Figure 1. 621S Reference Phase Noise 62fs  
(12kHz to 20MHz)  
The phase noise plots above show the low Additive Jitter of the 621S high-performance buffer. With an integration range of  
12kHz to 20MHz, the reference input has about 62fs of RMS phase jitter while the output of 621S has about 77fs of RMS phase  
jitter. This results in a low Additive Phase Jitter of only 45fs.  
Test Load and Circuit  
50ohms  
5 inche  
s
Rs=33ohm  
CL = 5pF  
LOW SKEW 1 TO 4 CLOCK BUFFER  

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