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621S PDF预览

621S

更新时间: 2024-10-29 14:57:47
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瑞萨 - RENESAS /
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描述
Low Skew 1 to 4 Clock Buffer

621S 数据手册

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AC Electrical Characteristics  
VDD=1.8V ±5%, Ambient Temperature -40° to +105°C, unless stated otherwise  
Parameter  
Output Frequency  
Symbol  
Conditions  
5pF load, Note 4  
Min.  
Typ. Max. Units  
200  
1.0  
1.0  
2
MHz  
ns  
Output Clock Rise Time  
Output Clock Fall Time  
Start-up Time  
tOR  
tOF  
0.36 to 1.44 V  
1.44 to 0.36V  
0.6  
0.6  
ns  
tSTART-UP Part start-up time for valid outputs after VDD  
ramp-up  
ms  
Propagation Delay  
135 MHz, Note 1  
1.5  
2
4
0.05  
65  
3
ns  
ps  
Buffer Additive Phase Jitter, RMS  
Output to Output Skew  
Output Enable Time  
125MHz, Integration range: 12kHz–20MHz  
Rising edges at VDD/2, Note 2  
50  
ps  
tEN  
CL < 5pF  
CL < 5pF  
cycles  
cycles  
Output Disable Time  
tDIS  
3
VDD=2.5V ±5%, Ambient Temperature -40° to +105°C, unless stated otherwise  
Parameter  
Output Frequency  
Symbol  
Conditions  
5pF load, Note 4  
Min.  
Typ. Max. Units  
200  
1.0  
1.0  
2
MHz  
ns  
Output Clock Rise Time  
Output Clock Fall Time  
Start-up Time  
tOR  
tOF  
0.5 to 2.0V  
2.0 to 0.5V  
0.6  
0.6  
ns  
tSTART-UP Part start-up time for valid outputs after VDD  
ramp-up  
ms  
Propagation Delay  
135 MHz, Note 1  
1.8  
2.5  
50  
4.5  
0.05  
65  
3
ns  
ps  
Buffer Additive Phase Jitter, RMS  
Output to Output Skew  
Output Enable Time  
125MHz, Integration range: 12kHz–20MHz  
Rising edges at VDD/2, Note 2  
ps  
tEN  
CL < 5pF  
CL < 5pF  
cycles  
cycles  
Output Disable Time  
tDIS  
3
VDD=3.3 V ±5%, Ambient Temperature -40° to +105°C, unless stated otherwise  
Parameter  
Output Frequency  
Symbol  
Conditions  
5pF load, Note 4  
Min.  
Typ. Max. Units  
200  
1.0  
1.0  
2
MHz  
ns  
Output Clock Rise Time  
Output Clock Fall Time  
Start-up Time  
tOR  
tOF  
0.66 to 2.64V  
2.64 to 0.66V  
0.6  
0.6  
ns  
tSTART-UP Part start-up time for valid outputs after VDD  
ramp-up  
ms  
Propagation Delay  
135 MHz, Note 1  
1.5  
2
4
0.05  
65  
3
ns  
ps  
Buffer Additive Phase Jitter, RMS  
Output to Output Skew  
Output Enable Time  
125MHz, Integration range: 12kHz–20MHz  
Rising edges at VDD/2, Note 2  
50  
ps  
tEN  
CL < 5pF  
CL < 5pF  
cycles  
cycles  
Output Disable Time  
tDIS  
3
Notes:  
1. With rail to rail input clock.  
2. Between any 2 outputs with equal loading.  
3. Duty cycle on outputs will match incoming clock duty cycle. Consult IDT for tight duty cycle clock generators.  
4. With external series resistor of 33positioned close to each output pin.  
REVISION A 03/18/15  

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