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5V40512DVGI PDF预览

5V40512DVGI

更新时间: 2024-01-21 02:02:00
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
9页 213K
描述
Clock Generator, 133.3MHz, CMOS, PDSO8, 3 MM, ROHS COMPLIANT, MSOP-8

5V40512DVGI 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:MSOP包装说明:3 MM, ROHS COMPLIANT, MSOP-8
针数:8Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.84JESD-30 代码:S-PDSO-G8
JESD-609代码:e3长度:3 mm
湿度敏感等级:3端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
最大输出时钟频率:133.3 MHz封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP8,.19
封装形状:SQUARE封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
主时钟/晶体标称频率:50 MHz认证状态:Not Qualified
座面最大高度:1.1 mm子类别:Clock Generators
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

5V40512DVGI 数据手册

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DATASHEET  
LOCO™ PLL CLOCK MULTIPLIER  
IDT5V40512  
Description  
Features  
The IDT5V40512 is the most cost effective way to generate  
a high-quality, high frequency clock output and a reference  
clock from a lower frequency crystal or clock input. The  
name LOCO stands for Low Cost Oscillator, as it is  
designed to replace crystal oscillators in most electronic  
systems. Using Phase-Locked-Loop (PLL) techniques, the  
device uses a standard fundamental mode, inexpensive  
crystal to produce output clocks up to 133.3 MHz. With a  
reference output, this chip plus an inexpensive crystal can  
replace two oscillators  
Packaged as 8-pin SOIC or MSOP  
Available in Pb (lead ) free package  
Upgrade of popular ICS502 with zero ppm multiplication  
error  
Easy to cascade with other 5xx series  
Input crystal frequency of 5 - 27 MHz  
Input clock frequency of 2 - 50 MHz  
Output clock frequencies up to 133.3 MHz  
Compatible with all popular CPUs  
Duty cycle of 45/55 up to 133.3 MHz  
Mask option for nine selectable frequencies  
Operating voltage of 3.0 V  
Stored in the chip’s ROM is the ability to generate nine  
different multiplication factors, allowing one chip to output  
many common frequencies (see table on page 2).  
This product is intended for clock generation. It has low  
output jitter (variation in the output period), but input to  
output skew and jitter are not defined or guaranteed. For  
applications which require defined input to output skew, use  
the ICS570B.  
Industrial temperature version  
Advanced, low power CMOS process  
Block Diagram  
VDD  
PLL Clock  
Synthesis  
and Control  
Circuitry  
CLK  
REF  
2
S1, S0  
X1/ICLK  
Crystal or  
Clock input  
Crystal  
Oscillator  
X2  
Optional crystal  
capacitors  
GND  
IDT™ LOCO™ PLL CLOCK MULTIPLIER  
1
IDT5V40512  
REV D 51309  

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