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5V2310PGI PDF预览

5V2310PGI

更新时间: 2024-01-15 02:43:06
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
10页 91K
描述
Low Skew Clock Driver, 5V Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PDSO24, TSSOP-24

5V2310PGI 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP-24
针数:24Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.28
其他特性:ALSO OPERATES AT 3.3V SUPPLY系列:5V
输入调节:STANDARDJESD-30 代码:R-PDSO-G24
JESD-609代码:e0逻辑集成电路类型:LOW SKEW CLOCK DRIVER
最大I(ol):0.006 A湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:24实输出次数:10
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:SERIES-RESISTOR封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:TSSOP24,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
电源:2.5/3.3 VProp。Delay @ Nom-Sup:3.5 ns
传播延迟(tpd):3.5 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.1 ns子类别:Clock Drivers
最大供电电压 (Vsup):2.7 V最小供电电压 (Vsup):2.3 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
最小 fmax:200 MHzBase Number Matches:1

5V2310PGI 数据手册

 浏览型号5V2310PGI的Datasheet PDF文件第2页浏览型号5V2310PGI的Datasheet PDF文件第3页浏览型号5V2310PGI的Datasheet PDF文件第4页浏览型号5V2310PGI的Datasheet PDF文件第6页浏览型号5V2310PGI的Datasheet PDF文件第7页浏览型号5V2310PGI的Datasheet PDF文件第8页 
IDT5V2310  
INDUSTRIALTEMPERATURERANGE  
2.5VTO3.3VHIGHPERFORMANCECLOCKBUFFER  
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE-  
VDD = 3.3V ± 0.3V(1)  
Symbol  
tPLH  
Parameter  
Test Conditions  
f = 0MHz to 200MHz  
Min.  
Typ.(1)  
Max  
Unit  
CLK to Yx  
1.3  
2.8  
ns  
tPHL  
tSK(O)(2)  
tSK(P)  
tSK(PP)  
tR  
Output Skew, Yx to Yx  
Pulse Skew  
100  
250  
500  
2
ps  
ps  
Part-to-PartSkew  
RiseTime  
ps  
VO = 0.4V to 2V(3)  
VO = 2V to 0.4V(3)  
V(THRESHOLD) = VDD/2  
0.7  
0.7  
0.1  
0.4  
V/ns  
V/ns  
ns  
tF  
FallTime  
2
tSU  
G before CLK↓  
G after CLK↓  
tH  
NOTES:  
1. All typical values are at respective nominal VDD.  
2. This specification is only valid for equal loading of all outputs.  
3. Measured at 100MHz.  
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE-  
VDD = 2.5V ± 0.2V(1)  
Symbol  
tPLH  
Parameter  
Test Conditions  
f = 0MHz to 170MHz  
Min.  
Typ.(1)  
Max  
Unit  
CLK to Yx  
1.5  
3.5  
ns  
tPHL  
tSK(O)(2)  
tSK(P)  
tSK(PP)  
tR  
Output Skew, Yx to Yx  
Pulse Skew  
100  
400  
600  
1.4  
1.4  
ps  
ps  
Part-to-PartSkew  
RiseTime  
ps  
VO = 0.4V to 1.7V(3)  
VO = 1.7V to 0.4V(3)  
V(THRESHOLD) = VDD/2  
0.5  
0.5  
0.1  
0.4  
V/ns  
V/ns  
ns  
tF  
FallTime  
tSU  
G before CLK↓  
G after CLK↓  
tH  
NOTES:  
1. All typical values are at respective nominal VDD.  
2. This specification is only valid for equal loading of all outputs.  
3. Measured at 100MHz.  
5

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