Datasheet > 5V2528APGI8

5V2528APGI8

更新时间： 2024-02-25 10:19:12

品牌	Logo	应用领域
艾迪悌 - IDT		光电二极管
页数	文件大小	规格书
7页	62K
描述
Clock Driver, PDSO28

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5V2528APGI8 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.92	Is Samacsys：	N
JESD-30 代码：	R-PDSO-G28	JESD-609代码：	e0
最大I（ol）：	0.012 A	湿度敏感等级：	1
端子数量：	28	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装等效代码：	TSSOP28,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	240	电源：	2.5/3.3,3.3 V
认证状态：	Not Qualified	子类别：	Clock Drivers
表面贴装：	YES	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn85Pb15)	端子形式：	GULL WING
端子节距：	0.635 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	20	Base Number Matches：	1

5V2528APGI8 数据手册

IDT5V2528/A

2.5/3.3VPHASE-LOCKLOOPCLOCKDRIVER

INDUSTRIALTEMPERATURERANGE

2.5V / 3.3V PHASE-LOCK

LOOP CLOCK DRIVER

ZERO DELAY BUFFER

IDT5V2528/A

The IDT5V2528 inputs, PLL core, Y0, Y1, andFBOUT buffers operate from

the 3.3V VDD and AVDD power supply pins.

FEATURES:

• Operates at 3.3V VDD/AVDD and 2.5V/3.3V VDDQ

• 1:10 fanout

One bank of ten outputs provide low-skew, low-jitter copies of CLK. Of

the ten outputs, up to seven may be configured for 2.5V or 3.3V LVTTL

outputs. The number of 2.5V outputs is controlled by 3-level input signals

G_CtrlandT_Ctrl, andbyconnectingtheappropriateVDDQ pinsto2.5Vor

3.3V. The 3-level input signals may be hard-wired to high-mid-low levels.

Outputsignaldutycyclesareadjustedto50percent,independentoftheduty

cycleatCLK. TheoutputscanbeenabledordisabledviatheG_Ctrl input.

When the G_Ctrl input is mid or high, the outputs switch in phase and

frequencywithCLK;whentheG_Ctrlislow, alloutputs(exceptFBOUT)are

disabledtothelogic-lowstate.

UnlikemanyproductscontainingPLLs,theIDT5V2528doesnotrequire

external RC networks. The loop filter for the PLL is included on-chip,

minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the IDT5V2528 requires a

stabilization time to achieve phase lock of the feedback signal to the

referencesignal.Thisstabilizationtimeisrequired,followingpowerupand

• 3-level inputs for output control

• External feedback (FBIN) pin is used to synchronize the

outputs to the clock input signal

• No external RC network required for PLL loop stability

• Configurable 2.5V or 3.3V LVTTL outputs

• tPD Phase Error at 100MHz to 166MHz: ±150ps

• Jitter (peak-to-peak) at 133MHz and 166MHz: ±75ps

• Spread spectrum compatible

• Operating Frequency:

−

Std: 25MHz to 140MHz

A: 25MHz to 167MHz

−

• Available in TSSOP package

DESCRIPTION:

TheIDT5V2528isahighperformance, low-skew, low-jitter, phase-lock application of a fixed-frequency, fixed-phase signal at CLK, as well as

loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency following any changes to the PLL reference or feedback signals. The PLL

and phase, the feedback (FBOUT) output to the clock (CLK) input signal. can be bypassed for test purposes by strapping AVDD to ground.

FUNCTIONALBLOCKDIAGRAM

G_Ctrl

T_Ctrl

TY0, V^DDQpin 4

TY1, VDDQ pin 25

TY2, V^DDQpin 25

TY3, V^DDQpin 15

TY4, V^DDQpin 15

MODE

SELECT

TY5, VDDQ pin 11

TY6, V^DDQpin 11

TY7, V^DDQpin 11

Y0, V^DDpin 21

CLK

PLL

FBIN

AV^DD

Y1, V^DDpin 21

FBOUT, V^DDpin 21

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

INDUSTRIAL TEMPERATURE RANGE

JUNE 2003

2002 Integrated Device Technology, Inc.

DSC 5971/11

12 3 4 5 6 7

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