IDT5V2528/A
2.5/3.3VPHASE-LOCKLOOPCLOCKDRIVER
INDUSTRIALTEMPERATURERANGE
2.5V / 3.3V PHASE-LOCK
LOOP CLOCK DRIVER
ZERO DELAY BUFFER
IDT5V2528/A
TheIDT5V2528inputs,PLLcore,Y0,Y1,andFBOUT buffers operate from
the 3.3V VDD and AVDD power supply pins.
FEATURES:
• Operates at 3.3V VDD/AVDD and 2.5V/3.3V VDDQ
• 1:10 fanout
One bankoftenoutputs provide low-skew,low-jittercopies ofCLK. Of
the ten outputs, up to seven may be configured for 2.5V or 3.3V LVTTL
outputs. Thenumberof2.5Voutputs is controlledby3-levelinputsignals
G_CtrlandT_Ctrl,andbyconnectingtheappropriateVDDQ pins to2.5Vor
3.3V. The3-levelinputsignals maybehard-wiredtohigh-mid-lowlevels.
Outputsignaldutycyclesareadjustedto50percent,independentoftheduty
cycleatCLK.Theoutputs canbeenabledordisabledviatheG_Ctrl input.
When the G_Ctrl input is mid or high, the outputs switch in phase and
frequencywithCLK;whentheG_Ctrlislow,alloutputs(exceptFBOUT)are
disabledtothelogic-lowstate.
UnlikemanyproductscontainingPLLs,theIDT5V2528doesnotrequire
external RC networks. The loop filter for the PLL is included on-chip,
minimizingcomponentcount,boardspace,andcost.
Because it is based on PLL circuitry, the IDT5V2528 requires a
stabilization time to achieve phase lock of the feedback signal to the
referencesignal.Thisstabilizationtimeisrequired,followingpowerupand
• 3-level inputs for output control
• External feedback (FBIN) pin is used to synchronize the
outputs to the clock input signal
• No external RC network required for PLL loop stability
• Configurable 2.5V or 3.3V LVTTL outputs
• tPD Phase Error at 100MHz to 166MHz: ±150ps
• Jitter (peak-to-peak) at 133MHz and 166MHz: ±75ps
• Spread spectrum compatible
• Operating Frequency:
−
−
Std: 25MHz to 140MHz
A: 25MHz to 167MHz
• Available in TSSOP package
DESCRIPTION:
TheIDT5V2528is ahighperformance,low-skew,low-jitter,phase-lock application of a fixed-frequency, fixed-phase signal at CLK, as well as
loop(PLL)clockdriver.Ituses a PLLtopreciselyalign,inbothfrequency followinganychanges tothe PLLreference orfeedbacksignals.The PLL
andphase,the feedback(FBOUT)outputtothe clock(CLK)inputsignal. can be bypassed for test purposes by strapping AVDD to ground.
FUNCTIONALBLOCKDIAGRAM
28
G_Ctrl
3
1
T_Ctrl
TY0, VDDQ pin 4
TY1, VDDQ pin 25
26
24
TY2, VDDQ pin 25
TY3, VDDQ pin 15
TY4, VDDQ pin 15
MODE
SELECT
17
16
13
TY5, VDDQ pin 11
TY6, VDDQ pin 11
12
10
6
7
TY7, VDDQ pin 11
Y0, VDD pin 21
CLK
PLL
20
19
FBIN
AVDD
Y1, VDD pin 21
5
22
FBOUT, VDD pin 21
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
OCTOBER 2008
1
c
2002 Integrated Device Technology, Inc.
DSC 5971/12