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5V2528APGGI PDF预览

5V2528APGGI

更新时间: 2024-01-20 14:55:43
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
9页 155K
描述
TSSOP-28, Tube

5V2528APGGI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:GREEN, TSSOP-28针数:28
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.81
系列:5V输入调节:STANDARD
JESD-30 代码:R-PDSO-G28JESD-609代码:e3
长度:9.7 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
最大I(ol):0.012 A湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:28实输出次数:10
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP28,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:2.5/3.3,3.3 V认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.25 ns座面最大高度:1.2 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
最小 fmax:167 MHzBase Number Matches:1

5V2528APGGI 数据手册

 浏览型号5V2528APGGI的Datasheet PDF文件第2页浏览型号5V2528APGGI的Datasheet PDF文件第3页浏览型号5V2528APGGI的Datasheet PDF文件第4页浏览型号5V2528APGGI的Datasheet PDF文件第5页浏览型号5V2528APGGI的Datasheet PDF文件第6页浏览型号5V2528APGGI的Datasheet PDF文件第7页 
2.5V / 3.3V PHASE-LOCK  
LOOP CLOCK DRIVER  
IDT5V2528/A  
NRND  
ZERO DELAY BUFFER  
NOT RECOMMENDED FOR NEW DESIGNS  
PLL core, Y0, Y1, and FBOUT buffers operate from the 3.3V VDD and AVDD power  
supply pins.  
FEATURES:  
• Operates at 3.3V VDD/AVDD and 2.5V/3.3V VDDQ  
• 1:10 fanout  
One bank of ten outputs provide low-skew, low-jitter copies of CLK. Of the ten  
outputs,uptosevenmaybeconfiguredfor2.5Vor3.3VLVTTLoutputs. Thenumber  
of 2.5V outputs is controlled by 3-level input signals G_Ctrl and T_Ctrl, and by  
connectingtheappropriateVDDQ pinsto2.5Vor3.3V. The3-levelinputsignalsmay  
be hard-wired to high-mid-low levels. Output signal duty cycles are adjusted to  
50 percent, independent of the duty cycle at CLK. The outputs can be enabled or  
disabledviatheG_Ctrl input.WhentheG_Ctrlinputismidorhigh,theoutputsswitch  
inphaseandfrequencywithCLK;whentheG_Ctrlislow,alloutputs(exceptFBOUT)  
are disabled to the logic-low state.  
UnlikemanyproductscontainingPLLs,theIDT5V2528doesnotrequireexternal  
RCnetworks. TheloopfilterforthePLLisincludedon-chip, minimizingcomponent  
count, board space, and cost.  
BecauseitisbasedonPLLcircuitry,theIDT5V2528requiresastabilizationtime  
toachievephaselockofthefeedbacksignaltothereferencesignal.Thisstabilization  
timeisrequired,followingpowerupandapplicationofafixed-frequency,fixed-phase  
signal at CLK, as well as following any changes to the PLL reference or feedback  
signals. ThePLLcanbebypassedfortestpurposesbystrappingAVDDtoground.  
• 3-level inputs for output control  
• External feedback (FBIN) pin is used to synchronize the  
outputs to the clock input signal  
• No external RC network required for PLL loop stability  
• Configurable 2.5V or 3.3V LVTTL outputs  
• tPD Phase Error at 100MHz to 166MHz: ±150ps  
• Jitter (peak-to-peak) at 133MHz and 166MHz: ±75ps  
• Spread spectrum compatible  
• Operating Frequency:  
-
Std: 25MHz to 140MHz  
- A: 25MHz to 167MHz  
• Available in TSSOP package  
NOT RECOMMENDED FOR NEW DESIGNS  
DESCRIPTION:  
The IDT5V2528 is a high performance, low-skew, low-jitter, phase-lock loop  
(PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase,  
thefeedback(FBOUT)outputtotheclock(CLK)inputsignal.TheIDT5V2528inputs,  
FUNCTIONALBLOCKDIAGRAM  
28  
G_Ctrl  
3
1
T_Ctrl  
TY0, VDDQ pin 4  
26  
TY1, VDDQ pin 25  
24  
TY2, VDDQ pin 25  
MODE  
SELECT  
17  
TY3, VDDQ pin 15  
16  
TY4, VDDQ pin 15  
13  
TY5, VDDQ pin 11  
12  
TY6, VDDQ pin 11  
10  
6
7
TY7, VDDQ pin 11  
CLK  
PLL  
20  
Y0, VDD pin 21  
FBIN  
AVDD  
19  
Y1, VDD pin 21  
5
22  
FBOUT, VDD pin 21  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
MAY 2013  
INDUSTRIAL TEMPERATURE RANGE  
1
c
2013 Integrated Device Technology, Inc.  
DSC 5971/12  

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