IDT5V2528/A
2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER
INDUSTRIAL TEMPERATURE RANGE
2.5V / 3.3V PHASE-LOCK
LOOP CLOCK DRIVER
IDT5V2528/A
NRND
ZERO DELAY BUFFER
NOT RECOMMENDED FOR NEW DESIGNS
PLL core, Y0, Y1, and FBOUT buffers operate from the 3.3V VDD and AVDD power
supply pins.
FEATURES:
• Operates at 3.3V VDD/AVDD and 2.5V/3.3V VDDQ
• 1:10 fanout
One bank of ten outputs provide low-skew, low-jitter copies of CLK. Of the ten
outputs,uptosevenmaybeconfiguredfor2.5Vor3.3VLVTTLoutputs. Thenumber
of 2.5V outputs is controlled by 3-level input signals G_Ctrl and T_Ctrl, and by
connectingtheappropriateVDDQ pinsto2.5Vor3.3V. The3-levelinputsignalsmay
be hard-wired to high-mid-low levels. Output signal duty cycles are adjusted to
50 percent, independent of the duty cycle at CLK. The outputs can be enabled or
disabledviatheG_Ctrl input.WhentheG_Ctrlinputismidorhigh,theoutputsswitch
inphaseandfrequencywithCLK;whentheG_Ctrlislow,alloutputs(exceptFBOUT)
are disabled to the logic-low state.
UnlikemanyproductscontainingPLLs,theIDT5V2528doesnotrequireexternal
RCnetworks. TheloopfilterforthePLLisincludedon-chip, minimizingcomponent
count, board space, and cost.
BecauseitisbasedonPLLcircuitry,theIDT5V2528requiresastabilizationtime
toachievephaselockofthefeedbacksignaltothereferencesignal.Thisstabilization
timeisrequired,followingpowerupandapplicationofafixed-frequency,fixed-phase
signal at CLK, as well as following any changes to the PLL reference or feedback
signals. ThePLLcanbebypassedfortestpurposesbystrappingAVDDtoground.
• 3-level inputs for output control
• External feedback (FBIN) pin is used to synchronize the
outputs to the clock input signal
• No external RC network required for PLL loop stability
• Configurable 2.5V or 3.3V LVTTL outputs
• tPD Phase Error at 100MHz to 166MHz: ±150ps
• Jitter (peak-to-peak) at 133MHz and 166MHz: ±75ps
• Spread spectrum compatible
• Operating Frequency:
-
Std: 25MHz to 140MHz
- A: 25MHz to 167MHz
• Available in TSSOP package
• NOT RECOMMENDED FOR NEW DESIGNS
DESCRIPTION:
The IDT5V2528 is a high performance, low-skew, low-jitter, phase-lock loop
(PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase,
thefeedback(FBOUT)outputtotheclock(CLK)inputsignal.TheIDT5V2528inputs,
FUNCTIONALBLOCKDIAGRAM
28
G_Ctrl
3
1
T_Ctrl
TY0, VDDQ pin 4
26
TY1, VDDQ pin 25
24
TY2, VDDQ pin 25
MODE
SELECT
17
TY3, VDDQ pin 15
16
TY4, VDDQ pin 15
13
TY5, VDDQ pin 11
12
TY6, VDDQ pin 11
10
6
7
TY7, VDDQ pin 11
CLK
PLL
20
Y0, VDD pin 21
FBIN
AVDD
19
Y1, VDD pin 21
5
22
FBOUT, VDD pin 21
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
MAY 2013
INDUSTRIAL TEMPERATURE RANGE
1
c
2013 Integrated Device Technology, Inc.
DSC 5971/12