Datasheet > 5V2305SNTGK

5V2305SNTGK

更新时间： 2024-02-09 14:56:00

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
10页	126K
描述
High-Performance 1 to 5 Clock Buffer

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技术参数
数据手册

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5V2305SNTGK 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Preview	零件包装代码：	DFN
包装说明：	,	针数：	10
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.72	JESD-609代码：	e3
湿度敏感等级：	1	峰值回流温度（摄氏度）：	260
端子面层：	Tin (Sn)	处于峰值回流温度下的最长时间：	NOT SPECIFIED
Base Number Matches：	1

5V2305SNTGK 数据手册

5V2305S DATASHEET

Pin Assignments

GND

VDD

ICLK

VDD

GND

ICLK

GND

VDD

GND

VDD

GND

VDD

10-pin DFN (2x2mm)

16-pin (173 mil) TSSOP

Pin Descriptions

Pin Name

Pin Number

Pin Type

Pin Description

16-pin TSSOP 10-pin DFN

VDD

GND

ICLK

2, 7, 10, 14, 15

1, 6

Power DC power supply. Connect to 1.8V to 3.3V.

Power Power supply ground.

1, 4, 8, 12

Input

Reference input clock.

Output Clock Output 0. Same frequency as CLKIN.

Output Clock Output 1. Same frequency as CLKIN.

Output Clock Output 2. Same frequency as CLKIN.

Output Clock Output 3. Same frequency as CLKIN.

Output Clock Output 4. Same frequency as CLKIN.

Active High Output Enable pin. When this pin is high, all outputs are

enabled and active. When this pin is low, all outputs are driven low.

Input

External Components

A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01µF should be

connected between VDD on pin 2 and GND on pin 4, as close to the device as possible. A 33 series terminating resistor may

be used on each clock output if the trace is longer than 1 inch.

To achieve the low output skew that the 5V2305S is capable of, careful attention must be paid to board layout. Essentially, all

five outputs must have identical terminations, identical loads and identical trace geometries. If they do not, the output skew will

be degraded. For example, using a 30 series termination on one output (with 33 on the others) will cause at least 15 ps of

skew.

HIGH-PERFORMANCE 1 TO 5 CLOCK BUFFER

AUGUST 1, 2016

123 4 5 6 7...10

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