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5P49V5901A045NLGI8

更新时间： 2024-02-05 09:30:02
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
37页 435K
描述
Clock Generator, PQCC24

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5P49V5901A045NLGI8 技术参数

是否Rohs认证： 符合生命周期：Obsolete
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.84
JESD-30 代码：S-PQCC-N24端子数量：24
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：QCCN
封装等效代码：LCC24,.16SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER电源：1.8/3.3 V
认证状态：Not Qualified子类别：Clock Generators
最大压摆率：47 mA表面贴装：YES
温度等级：INDUSTRIAL端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
Base Number Matches：1

5P49V5901A045NLGI8 数据手册

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5P49V5901A DATASHEET  
Table 1:Pin Descriptions  
Number  
Name  
Type  
Description  
Internal  
Pull-down  
1
CLKIN  
Input  
Differential clock input. Weak 100kohms internal pull-down.  
Internal  
Pull-down  
2
3
CLKINB  
XOUT  
Input  
Input  
Complementary differential clock input. Weak 100kohms internal pull-down.  
Crystal Oscillator interface output.  
Crystal Oscillator interface input, or single-ended LVCMOS clock input. Ensure that  
the input voltage is 1.2V max.Refer to the section “Overdriving the XIN/REF  
Interface”.  
4
5
XIN/REF  
VDDA  
Input  
Analog functions power supply pin.Connect to 1.8V to 3.3V. VDDA and VDDD should  
have the same voltage applied.  
Power  
Input clock select. Selects the active input reference source in manual switchover  
mode.  
Internal  
Pull-down  
6
CLKSEL  
Input  
Input  
0 = XIN/REF, XOUT (default)  
1 = CLKIN, CLKINB  
CLKSEL Polarity can be changed by I2C programming as shown in Table 4.  
Enables/disables the outputs (OE) or powers down the chip (SD). The SH bit  
controls the configuration of the SD/OE pin. The SH bit needs to be high for SD/OE  
pin to be configured as SD. The SP bit (0x02) controls the polarity of the signal to be  
either active HIGH or LOW only when pin is configured as OE (Default is active  
LOW.) Weak internal pull down resistor. When configured as SD, device is shut  
down, differential outputs are driven high/low, and the single-ended LVCMOS  
outputs are driven low. When configured as OE, and outputs are disabled, the  
outputs can be selected to be tri-stated or driven high/low, depending on the  
programming bits as shown in the SD/OE Pin Function Truth table.  
Internal  
Pull-down  
7
SD/OE  
Internal  
Configuration select pin, or I2C SDA input as selected by OUT0_SEL_I2CB. Weak  
8
9
SEL1/SDA  
SEL0/SCL  
Input  
Input  
Pull-down internal pull down resistor.  
Internal  
Configuration select pin, or I2C SCL input as selected by OUT0_SEL_I2CB. Weak  
Pull-down internal pull down resistor.  
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for  
OUT4/OUT4B.  
10  
11  
12  
VDDO  
4
Power  
Output  
Output  
OUT4  
Output Clock 4. Please refer to the Output Drivers section for more details.  
Complementary Output Clock 4. Please refer to the Output Drivers section for more  
details.  
OUT4B  
Complementary Output Clock 3. Please refer to the Output Drivers section for more  
details.  
13  
14  
15  
OUT3B  
OUT3  
Output  
Output  
Power  
Output Clock 3. Please refer to the Output Drivers section for more details.  
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for  
OUT3/OUT3B.  
VDDO  
3
Complementary Output Clock 2. Please refer to the Output Drivers section for more  
details.  
16  
17  
18  
OUT2B  
OUT2  
Output  
Output  
Power  
Output Clock 2. Please refer to the Output Drivers section for more details.  
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for  
OUT2/OUT2B.  
VDDO  
2
Complementary Output Clock 1. Please refer to the Output Drivers section for more  
details.  
19  
20  
21  
OUT1B  
OUT1  
Output  
Output  
Power  
Output Clock 1. Please refer to the Output Drivers section for more details.  
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for  
OUT1/OUT1B.  
VDDO  
1
REVISION F 03/10/15  
3
PROGRAMMABLE CLOCK GENERATOR  
1234567...37

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