Datasheet > 5P49V5907ADDDNDGI

5P49V5907ADDDNDGI

更新时间： 2024-01-28 17:22:28

品牌	Logo	应用领域
艾迪悌 - IDT		时钟外围集成电路晶体
页数	文件大小	规格书
30页	424K
描述
Processor Specific Clock Generator

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5P49V5907ADDDNDGI 技术参数

生命周期：	Obsolete	包装说明：	VFQFPN-40
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.74
JESD-30 代码：	S-XQCC-N40	长度：	5 mm
端子数量：	40	最高工作温度：	85 °C
最低工作温度：	-40 °C	最大输出时钟频率：	350 MHz
封装主体材料：	UNSPECIFIED	封装代码：	HVQCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
主时钟/晶体标称频率：	25 MHz	座面最大高度：	1 mm
最大供电电压：	1.89 V	最小供电电压：	1.71 V
标称供电电压：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	NO LEAD	端子节距：	0.4 mm
端子位置：	QUAD	宽度：	5 mm
uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, PROCESSOR SPECIFIC	Base Number Matches：	1

5P49V5907ADDDNDGI 数据手册

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Programmable Clock Generator

5P49V5907

DATASHEET

Description

Features

The 5P49V5907 is a programmable clock generator intended

for high performance consumer, networking, industrial,

computing, and data-communications applications.

Configurations may be stored in on-chip One-Time

• Generates up to four independent output frequencies with a

total of 7 differential outputs and one reference output

• Supports multiple differential output I/O standards:

– Three universal outputs pairs with each configurable

as one differential output pair (LVDS, LVPECL or

regular HCSL) or two LVCMOS outputs. Frequency of

each output pair can be individually programmed

Programmable (OTP) memory or changed using I C

interface. This is IDTs fifth generation of programmable clock

technology (VersaClock 5).

The frequencies are generated from a single reference clock

or crystal. Two select pins allow up to 4 different

– Four copies of Low Power HCSL(LP-HCSL) outputs.

• Programmable frequency:

configurations to be programmed and accessible using

processor GPIOs or bootstrapping. The different selections

may be used for different operating modes (full function,

partial function, partial power-down), regional standards (US,

Japan, Europe) or system production margin testing.

– See Output Features and Descriptions for details

• One reference LVCMOS output clock

• High performance, low phase noise PLL, <0.7 ps RMS

typical phase jitter on outputs:

The device may be configured to use one of two I C

– PCIe Gen1, 2, 3 compliant clock capability

– USB 3.0 compliant clock capability

– 1 GbE and 10 GbE

addresses to allow multiple devices to be used in a system.

Pin Assignment

• Four fractional output dividers (FODs)

• Independent Spread Spectrum capability from each

fractional output divider (FOD)

• Four banks of internal non-volatile in-system

programmable or factory programmable OTP memory

• I C serial programming interface

• Input frequency ranges:

40 39 38 37 36

34 33 32 31

– LVCMOS Reference Clock Input (XIN/REF) – 1MHz

to 200MHz

V_DDO

XOUT

XIN/REF

V_DDA

OUT2

– Crystal frequency range: 8MHz to 40MHz

OUT2B

• Output frequency ranges:

V_DD

– LVCMOS Clock Outputs – 1MHz to 200MHz

V_DDO

V_DD

EPAD

– LP-HCSL Clock Outputs – 1MHz to 200MHz

V_{DD_CORE}

OUT3

OUT3B

OUT7

OUT7B

– Other Differential Clock Outputs – 1MHz to 350MHz

OUT6

OUT6B

SD/OE

• Programmable loop bandwidth

• Programmable crystal load capacitance

• Power-down mode

17 18

19 20

13 14 15 16

• Mixed voltage operation:

– 1.8V core

– 1.8V VDDO for 4 LP-HCSL outputs

– 1.8V to 3.3V VDDO for other outputs

(3 programmable differential outputs and 1 reference

output)

40-pin VFQFPN

– See Pin Descriptions for details

• Packaged in 40-pin 5mm x 5mm VFQFPN (NDG40)

• -40° to +85°C industrial temperature operation

5P49V5907 REVISION B 07/13/15

12 3 4 5 6 7...30

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