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5P49V5907ADDDNDGI

更新时间： 2024-01-13 10:43:52
品牌 Logo 应用领域
艾迪悌 - IDT 时钟外围集成电路晶体
页数 文件大小 规格书
30页 424K
描述
Processor Specific Clock Generator

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5P49V5907ADDDNDGI 技术参数

生命周期：Obsolete包装说明：VFQFPN-40
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.74
JESD-30 代码：S-XQCC-N40长度：5 mm
端子数量：40最高工作温度：85 °C
最低工作温度：-40 °C最大输出时钟频率：350 MHz
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
主时钟/晶体标称频率：25 MHz座面最大高度：1 mm
最大供电电压：1.89 V最小供电电压：1.71 V
标称供电电压：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：NO LEAD端子节距：0.4 mm
端子位置：QUAD宽度：5 mm
uPs/uCs/外围集成电路类型：CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches：1

5P49V5907ADDDNDGI 数据手册

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5P49V5907 DATASHEET  
Table 1:Pin Descriptions  
Number  
Name  
Type  
Description  
1
2
3
NC  
Input  
Input  
Input  
Do not connect  
XOUT  
Crystal Oscillator interface output.  
XIN/REF  
Crystal Oscillator interface input, or single-ended LVCMOS clock input. Ensure  
that the input voltage is 1.2V max. Refer to the section “Overdriving the  
XIN/REFInterfac e”.  
4
5
VDDA  
VDDO  
OUT7  
Power  
Power  
Output  
Output  
Output  
Output  
Input  
Analog functions power supply pin. Connect to 1.8V.  
Connect to 1.8V. Power pin for outputs 3, 5-7  
6
Output Clock 7. Low-Power HCSL (LP-HCSL) output.  
7
OUT7B  
OUT6  
Complementary Output Clock 7. Low-Power HCSL (LP-HCSL) output..  
Output Clock 6. Low-Power HCSL (LP-HCSL) output.  
8
9
OUT6B  
SD/OE  
Complementary Output Clock 6. Low-Power HCSL (LP-HCSL) output..  
10  
Internal Pull- Enables/disables the outputs (OE) or powers down the chip (SD). The SH bit  
down  
controls the configuration of the SD/OE pin. The SH bit needs to be high for  
SD/OE pin to be configured as SD. The SP bit (0x02) controls the polarity of  
the signal to be either active HIGH or LOW only when pin is configured as OE  
(Default is active LOW.) Weak internal pull down resistor. When configured as  
SD, device is shut down, differential outputs are driven high/low, and the  
single-ended LVCMOS outputs are driven low. When configured as OE, and  
outputs are disabled, the outputs can be selected to be tri-stated or driven  
high/low, depending on the programming bits as shown in the SD/OE Pin  
Function Truth table.  
11  
12  
SEL1/SDA  
SEL0/SCL  
Input  
Input  
Internal Pull- Configuration select pin, or I2C SDA input as selected by OUT0_SEL_I2CB.  
down Weak internal pull down resistor.  
Internal Pull- Configuration select pin, or I2C SCL input as selected by OUT0_SEL_I2CB.  
down  
Weak internal pull down resistor.  
Connect to 1.8V  
13  
14  
15  
16  
17  
VDD  
Power  
Power  
Output  
Output  
Input  
VDDO  
OUT5  
OUT5B  
Connect to 1.8V. Power pin for outputs 3, 5-7.  
Output Clock 5. Low-Power HCSL (LP-HCSL) output.  
Complementary Output Clock 5. Low-Power HCSL (LP-HCSL) output.  
Internal Pull- Active low Output Enable pin for Outputs 3 and 5.  
OEB3,5  
down  
1=disable outputs, 0=enable outputs. This pin has internal pull-down.  
Connect to 1.8V to 3.3V. VDD supply for OUT4.  
18  
19  
20  
VDDO4  
OUT4  
Power  
Output  
Output  
Output Clock 4. Please refer to the Output Drivers section for more details.  
OUT4B  
Complementary Output Clock 4. Please refer to the Output Drivers section for  
more details.  
21  
22  
23  
24  
25  
26  
27  
28  
NC  
Do not connect  
—
—
NC  
Do not connect  
OUT3B  
OUT3  
VDD_Core  
VDD  
Output  
Output  
Power  
Power  
Power  
Output  
Complementary Output Clock 3. Low-Power HCSL (LP-HCSL) output.  
Output Clock 3. HCSL Low-Power HCSL (LP-HCSL) output..  
Connect to 1.8V  
Connect to 1.8V  
Connect to 1.8V  
VDD  
OUT2B  
Complementary Output Clock 2. Please refer to the Output Drivers section for  
more details.  
29  
30  
31  
OUT2  
Output  
Power  
Output  
Output Clock 2. Please refer to the Output Drivers section for more details.  
VDDO2  
OUT1B  
Connect to 1.8V to 3.3V. VDD supply for OUT2.  
Complementary Output Clock 1. Please refer to the Output Drivers section for  
more details.  
32  
33  
34  
OUT1  
Output  
Power  
Input  
Output Clock 1. Please refer to the Output Drivers section for more details.  
VDDO1  
Connect to 1.8V to 3.3V. VDD supply for OUT1.  
Internal Pull- Active low Output Enable pin for Outputs 6 and 7.  
OEB6,7  
down  
1=disable outputs, 0=enable outputs. This pin has internal pull-down.  
Do not connect  
35  
NC  
—
REVISION B 07/13/15  
3
PROGRAMMABLE CLOCK GENERATOR  
1234567...30

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