Datasheet > 5P49V5901A045NLGI8

5P49V5901A045NLGI8

更新时间： 2024-02-01 20:31:49

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
37页	435K
描述
Clock Generator, PQCC24

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5P49V5901A045NLGI8 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.84
JESD-30 代码：	S-PQCC-N24	端子数量：	24
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCN
封装等效代码：	LCC24,.16SQ,20	封装形状：	SQUARE
封装形式：	CHIP CARRIER	电源：	1.8/3.3 V
认证状态：	Not Qualified	子类别：	Clock Generators
最大压摆率：	47 mA	表面贴装：	YES
温度等级：	INDUSTRIAL	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	QUAD
Base Number Matches：	1

5P49V5901A045NLGI8 数据手册

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5P49V5901A DATASHEET

If OUT0_SEL_I2CB was 0 at POR, alternate configurations

can only be loaded via the I2C interface.

PLL Features and Descriptions

Spread Spectrum

Table 4: Input Clock Select

Input clock select. Selects the active input reference source in

manual switchover mode.

0 = XIN/REF, XOUT (default)

1 = CLKIN, CLKINB

To help reduce electromagnetic interference (EMI), the

5P49V5901A supports spread spectrum modulation. The

output clock frequencies can be modulated to spread energy

across a broader range of frequencies, lowering system EMI.

The 5P49V5901A implements spread spectrum using the

Fractional-N output divide, to achieve controllable modulation

rate and spreading magnitude. The Spread spectrum can be

applied to any output clock, any clock frequency, and any

spread amount from ±0.25% to ±2.5% center spread and

-0.5% to -5% down spread.

CLKSEL Polarity can be changed by I C programming as

shown in the table below.

PRIMSRC

CLKSEL

Source

XIN/REF

CLKIN, CLKINB

XIN/REF

Table 2: Loop Filter

PLL loop bandwidth range depends on the input reference

frequency (Fref) and can be set between the loop bandwidth

range as shown in the table below.

PRIMSRC is bit 1 of Register 0x13.

Input Reference

Loop

Frequency–Fref BandwidthMin Bandwidth Max

(MHz)

(kHz)

126

350

300

1000

Table 3: Configuration Table

This table shows the SEL1, SEL0 settings to select the

configuration stored in OTP. Four configurations can be stored

in OTP. These can be factory programmed or user

programmed.

OUT0_SEL_I2CB SEL1 SEL0

@ POR

I C

REG0:7 Config

Access

Yes

I2C

defaults

Yes

At power up time, the SEL0 and SEL1 pins must be tied to

either the VDDD/VDDA power supply so that they ramp with

that supply or are tied low (this is the same as floating the

pins). This will cause the register configuration to be loaded

that is selected according to Table 3 above. Providing that

OUT0_SEL_I2CB was 1 at POR and OTP register 0:7=0, after

the first 10mS of operation the levels of the SELx pins can be

changed, either to low or to the same level as VDDD/VDDA.

The SELx pins must be driven with a digital signal of < 300nS

Rise/Fall time and only a single pin can be changed at a time.

After a pin level change, the device must not be interrupted for

at least 1ms so that the new values have time to load and take

effect.

REVISION F 03/10/15

PROGRAMMABLE CLOCK GENERATOR

1 2 3 456 7 8...37

中文翻译

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