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5962R1322001VXC PDF预览

5962R1322001VXC

更新时间： 2024-01-19 14:11:32
品牌 Logo 应用领域
英特矽尔 - INTERSIL /
页数 文件大小 规格书
16页 657K
描述
1.5A, Rad Hard, Positive, High Voltage LDO

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5962R1322001VXC 技术参数

生命周期：Transferred包装说明：DFP,
Reach Compliance Code：compliant风险等级：5.67
最大回动电压 1：0.4 VJESD-30 代码：R-CDFP-F16
长度：10.414 mm功能数量：1
端子数量：16工作温度TJ-Max：150 °C
最大输出电流 1：1.5 A最大输出电压 1：12.7 V
最小输出电压 1：0.6 V封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：DFP封装形状：RECTANGULAR
封装形式：FLATPACK认证状态：Not Qualified
调节器类型：ADJUSTABLE POSITIVE SINGLE OUTPUT LDO REGULATOR筛选级别：MIL-PRF-38535 Class V
座面最大高度：2.92 mm表面贴装：YES
技术：BICMOS端子形式：FLAT
端子节距：1.27 mm端子位置：DUAL
总剂量：100k Rad(Si) V宽度：6.855 mm
Base Number Matches：1

5962R1322001VXC 数据手册

 浏览型号5962R1322001VXC的Datasheet PDF文件第4页浏览型号5962R1322001VXC的Datasheet PDF文件第5页浏览型号5962R1322001VXC的Datasheet PDF文件第6页浏览型号5962R1322001VXC的Datasheet PDF文件第8页浏览型号5962R1322001VXC的Datasheet PDF文件第9页浏览型号5962R1322001VXC的Datasheet PDF文件第10页 
ISL75052SEH  
Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the following specified conditions:  
V
= V  
OUT  
+ 0.5V, V  
OUT  
= 4.0V, C = C  
IN  
= 2x100µF 60mΩ, KEMET type T541X107N025AH or equivalent, T = +25°C, I = 0A. Applications must follow  
OUT J L  
IN  
thermal guidelines of the package to determine worst case junction temperature. Please refer to “Applications Information” on page 7 of the data sheet  
and Tech Brief TB379. Boldface limits apply over the operating temperature range, -55°C to +125°C. Pulse load techniques used by ATE to ensure T = T  
J
A
defines guaranteed limits. (Continued)  
MIN  
MAX  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
(Note 8) TYP (Note 8) UNITS  
DEVICE START-UP CHARACTERISTICS  
Enable Pin Characteristics  
Turn-on Threshold  
4.0V < V < 13.2V  
IN  
0.5  
0.8  
1.2  
1
V
Enable Pin Leakage Current  
V
= 13.2V, EN = 5.5V  
µA  
ms  
IN  
Enable Pin Propagation Delay (EN  
V
= 4.5V, V  
OUT  
= 4.0V, I  
= 1.5A,  
= 1.5A,  
0.5  
1.4  
1.1  
170  
1.0  
IN  
LOAD  
LOAD  
step 1.2V to V  
OUT  
= 100mV)  
C
= 22µF, C  
= 0.2µF  
OUT  
BYP  
Enable Pin Turn-on Delay  
(EN step 1.2V to PGOOD)  
V
C
= 4.5V, V  
= 4.0V, I  
3.0  
2.5  
ms  
ms  
mV  
IN  
OUT  
= 2x100µF, C  
= 0.2µF  
OUT  
BYP  
= 4.0V, I  
Enable Pin Turn-on Delay  
(EN step 1.2V to PGOOD)  
V
C
= 4.5V, V  
= 1.5A,  
IN  
OUT  
= 22µF, C  
LOAD  
= 0.2µF  
OUT  
BYP  
Hysteresis (Falling Threshold)  
PG Pin Characteristics  
4.0V < V < 13.2V  
75  
IN  
V
V
V
Error Flag Rising Threshold  
Error Flag Falling Threshold  
Error Flag Hysteresis  
83  
80  
88  
86  
2.5  
5
94  
91  
%V  
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
%V  
%V  
1.75  
Error Flag Low Voltage  
Error Flag Low Voltage  
Error Flag Leakage Current  
I
I
= 1mA  
100  
400  
1
mV  
SINK  
= 10mA  
5
mV  
µA  
SINK  
V
= 13.2V, PG = 5.5V  
IN  
8. Parameters with bold face MIN and/or MAX limits are 100% tested at -55°C, 25°C and 125°C.  
9. Limits established by characterization and are not production tested.  
10. Dropout is defined by the difference in supply V and V  
IN OUT  
when the supply produces a 2% drop in V from its nominal value.  
OUT  
11. Refer to thermal package guidelines in “Bottom Metal Mounting Guidelines” on page 8..  
12. OCP recovery overshoot should be within ±4% of the nominal VOUT setpoint.  
13. SET performance of <±5% at LET = 86MeV.cm2/mg has been evaluated at V  
0.1µF CDR04 X7R capacitor. Capacitor on BYP = 0.1µF CDR04 X7R.  
= >2.5V with C = C  
IN  
= 2x100µF 10V 60mΩ in parallel with  
OUT  
OUT  
OUTPUT CAPACITOR  
Applications Information  
Input Voltage Requirements  
It is recommended to use a combination of Tantalum and  
Ceramic capacitors to achieve a good volume to capacitance  
ratio. The recommended combination is a 2x100µF 60mΩ rated,  
KEMET T541 series tantalum capacitor, in parallel with a 0.1µF  
MIL-PRF-49470 ceramic capacitor to be connected to V  
Ground pins of the LDO with PCB traces no longer than 0.5cm.  
This RH LDO will work from a V in the range of 4.0V to 13.2V.  
IN  
The input supply can have a tolerance of as much as ±10% for  
conditions noted in the specification table. The minimum  
guaranteed input voltage is 4.0V. However, due to the nature of  
and  
OUT  
an LDO, V must be some margin higher than the output voltage  
plus dropout at the maximum rated current of the application if  
IN  
INPUT CAPACITOR  
It is recommended to use a combination of Tantalum and  
Ceramic capacitors to achieve a good capacitance to volume  
ratio. The recommended combination is a 2x100µF 60mΩ rated,  
KEMET T541 series tantalum capacitor in parallel with a 0.1µF  
active filtering (PSRR) is expected from V to V . The Dropout  
spec of this family of LDOs has been generously specified in  
order to allow design for efficient operation.  
IN OUT  
External Capacitor Requirements  
MIL-PRF-49470 ceramic capacitor to be connected to V and  
Ground pins of the LDO with PCB traces no longer than 0.5cm.  
IN  
GENERAL GUIDELINE  
Current Limit Protection  
External capacitors are required for proper operation. Careful  
attention must be paid to layout guidelines and selection of  
capacitor type and value to ensure optimal performance.  
The RH LDO incorporates protection against overcurrent due to  
any short or overload condition applied to the output pin. The  
current limit circuit performs as a constant current source when  
the output current exceeds the current limit threshold which can  
be adjusted by means of a resistor connected between the OCP  
FN8456.0  
May 29, 2013  
7
1...45678910...16

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