Datasheet > 5962F9096505Q9B

5962F9096505Q9B

更新时间： 2024-09-29 23:23:15

品牌	Logo	应用领域
其他 - ETC		可编程逻辑栅
页数	文件大小	规格书
25页	148K
描述
FPGA

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数据手册

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5962F9096505Q9B 数据手册

REVISIONS

LTR

DESCRIPTION

DATE (YR-MO-DA)

APPROVED

M. A. Frye

Add device type 02; editorial changes throughout. Redrawn.

93-06-23

94-06-30

Update boilerplate. Add device types 03 and 04. Add case outline

M. Editorial changes throughout.

M. A. Frye

Add 05 device. Removed some parameters from table IIB. Updated

boilerplate. ksr

98-04-06

98-07-10

Raymond Monnin

Added equation to footnote 2/, made corrections to table IB.

Changed sample size in paragraph 4.4.1. Removed (Dose Rate

Induced latchup testing) and (Dose Rate Upset testing) paragraphs.

Updated boilerplate. ksr

Change 1.3 Maximum junction temperature from 175 C to 150 C.

Added footnote 2/ to Figure 2 for the T and M case outlines. Add die

information per Appendix A. ksr

98-09-21

Raymond Monnin

REV

SHEET

REV

SHEET

REV STATUS

OF SHEETS

REV

SHEET

PREPARED BY

TIM H. NOH

PMIC N/A

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 42316

STANDARD

MICROCIRCUIT

DRAWING

CHECKED BY

KENNETH RICE

MICROCIRCUIT, MEMORY, DIGITAL, , CMOS,

FIELD PROGRAMMABLE GATE ARRAY,

2000 GATES,MONOLITHIC SILICON

APPROVED BY

TIM H. NOH

THIS DRAWING IS

AVAILABLE

FOR USE BY ALL

DEPARTMENTS

AND AGENCIES OF THE

DEPARTMENT OF DEFENSE

DRAWING APPROVAL DATE

92-06-23

SIZE

CAGE CODE

5962-90965

REVISION LEVEL

A 67268

AMSC N/A

SHEET

DSCC FORM 2233

APR 97

5962-E526-98

DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.

12 3 4 5 6 7...25

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