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5962F0620202 PDF预览

5962F0620202

更新时间: 2024-10-28 21:15:11
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 接口集成电路
页数 文件大小 规格书
17页 430K
描述
LINE RECEIVER

5962F0620202 技术参数

生命周期:Active包装说明:,
Reach Compliance Code:compliant风险等级:5.67
接口集成电路类型:LINE RECEIVER认证状态:Not Qualified
总剂量:300k Rad(Si) VBase Number Matches:1

5962F0620202 数据手册

 浏览型号5962F0620202的Datasheet PDF文件第2页浏览型号5962F0620202的Datasheet PDF文件第3页浏览型号5962F0620202的Datasheet PDF文件第4页浏览型号5962F0620202的Datasheet PDF文件第5页浏览型号5962F0620202的Datasheet PDF文件第6页浏览型号5962F0620202的Datasheet PDF文件第7页 
RHFLVDSR2D2  
Rad-hard dual LVDS driver-receiver  
Datasheet - production data  
Large input common mode: -4 V to +5 V  
Guaranteed up to 300 krad TID  
SEL immune up to 135 MeV.cm²/mg  
SET/SEU immune up to 32 MeV.cm²/mg  
Description  
Dual low voltage differential signaling (LVDS),  
driver receiver designed, packaged and qualified  
for use in aerospace environments in a low-power  
and fast-transmission standard, and operating at  
3.3 V power supply (3.6 V max operating and   
4.8 V AMR). The RHFLVDSR2D2 operates over a  
controlled impedance of 100-ohm transmission  
media that may be printed circuit board traces,  
back planes, or cables.  
Ceramic Flat-18  
The upper metallic lid is  
electrically connected to ground  
Features  
Dual drivers, TTL compatible inputs/LVDS  
outputs  
The circuit features an internal fail-safe function to  
ensure a known state in case of an input short  
circuit or floating input. All pins have cold spare  
buffers to ensure they are in high impedance  
Dual receivers, LVDS inputs/TTL compatible  
outputs  
Individual Enable/Disable function with high-  
impedance  
when V is tied to GND.  
CC  
ANSI TIA/EIA-644 compliant  
400 Mbps (200 MHz)  
The RHFLVDSR2D2 can operate over a large  
temperature range of -55 °C to +125 °C and it is  
housed in an hermetic Ceramic Flat-18 package.  
Cold spare on all pins  
Fail-safe function  
3.3 V operating power supply  
4.8 V absolute rating  
Power consumption: 50 mW at 3.3 V  
Hermetic package  
Table 1. Device summary  
Lead  
finish  
Reference  
SMD pin  
Quality level Package  
Mass EPPL(1) Temp. range  
Engineering  
RHFLVDSR2D2K1  
-
-
Ceramic  
model  
-55 °C to  
125 °C  
Gold  
-
Flat-18  
RHFLVDSR2D2K01V 5962F0620202 QML-V flight  
Target  
1. EPPL = ESA preferred part list  
October 2014  
DocID025372 Rev 2  
1/17  
This is information on a product in full production.  
www.st.com  
 

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