ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀꢁꢊ ꢃ ꢄꢅ ꢉꢆ ꢃꢇ
ꢋꢌ ꢍꢌ ꢎꢏꢉ ꢀꢌ ꢍ ꢐꢏꢉ ꢑꢒ ꢓ ꢆꢔ ꢀ ꢀꢓ ꢒ ꢀ
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006
Terminal Functions
CONDITIONS
WHEN
SIGNAL IS Z TYPE
TERMINAL
†
DESCRIPTION
TYPE
NAME
QTY
‡
PRIMARY-BUS INTERFACE
D31−D0
A23−A0
32
24
I/O/Z 32-bit data port
S
S
H
H
R
R
O/Z
O/Z
O/Z
I
24-bit address port
Read/write. R/W is high when a read is performed and low when a write is performed
over the parallel interface.
R/W
STRB
RDY
1
1
1
S
S
H
H
R
External-access strobe
Ready. RDY indicates that the external device is prepared for a transaction
completion.
Hold. When HOLD is a logic low, any ongoing transaction is completed. A23−A0,
D31−D0, STRB, and R/W are placed in the high-impedance state and all transac-
tions over the primary-bus interface are held until HOLD becomes a logic high or until
the NOHOLD bit of the primary-bus-control register is set.
HOLD
1
1
I
Hold acknowledge. HOLDA is generated in response to a logic low on HOLD. HOLDA
indicates that A23−A0, D31−D0, STRB, and R/W are in the high-impedance state
and that all transactions over the bus are held. HOLDA is high in response to a logic
high of HOLD or the NOHOLD bit of the primary-bus-control register is set.
HOLDA
O/Z
S
CONTROL SIGNALS
Reset. When RESET is a logic low, the device is in the reset condition. When RESET
becomes a logic high, execution begins from the location specified by the reset vector.
RESET
1
4
1
1
I
INT3−INT0
IACK
I
O/Z
I
External interrupts
Interrupt acknowledge. IACK is generated by the IACK instruction. IACK can be used
to indicate the beginning or the end of an interrupt-service routine.
S
MCBL/MP
Microcomputer boot-loader/microprocessor mode-select
Shutdown high impedance. When active, SHZ shuts down the device and places all
pins in the high-impedance state. SHZ is used for board-level testing to ensure that
no dual-drive conditions occur. CAUTION: A low on SHZ corrupts the device memory
and register contents. Reset the device with SHZ high to restore it to a known
operating condition.
SHZ
1
2
I
External flags. XF1 and XF0 are used as general-purpose I/Os or to support
interlocked processor instruction.
XF1, XF0
I/O/Z
S
R
SERIAL PORT 0 SIGNALS
CLKR0
CLKX0
1
1
I/O/Z Serial port 0 receive clock. CLKR0 is the serial shift clock for the serial port 0 receiver.
S
S
R
R
Serial port 0 transmit clock. CLKX0 is the serial shift clock for the serial port 0
I/O/Z
transmitter.
DR0
DX0
1
1
I/O/Z Data-receive. Serial port 0 receives serial data on DR0.
S
S
R
R
I/O/Z Data-transmit output. Serial port 0 transmits serial data on DX0.
Frame-synchronization pulse for receive. The FSR0 pulse initiates the data-receive
process using DR0.
FSR0
FSX0
1
1
I/O/Z
S
S
R
R
Frame-synchronization pulse for transmit. The FSX0 pulse initiates the data-transmit
process using DX0.
I/O/Z
TIMER SIGNALS
Timer clock 0. As an input, TCLK0 is used by timer 0 to count external pulses. As an
output, TCLK0 outputs pulses generated by timer 0.
TCLK0
TCLK1
1
1
I/O/Z
S
S
Timer clock 1. As an input, TCLK0 is used by timer 1 to count external pulses. As an
output, TCLK1 outputs pulses generated by timer 1.
I/O/Z
†
‡
I = input, O = output, Z = high-impedance state
S = SHZ active, H = HOLD active, R = RESET active
7
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