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5962-9317901MLA

更新时间： 2024-02-19 21:22:10
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
28页 462K
描述
CMOS, Complete 12-bit, 100 kHz, Sampling ADC with ±10V Input Signal Range

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中文翻译

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5962-9317901MLA 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：DIP
包装说明：DIP, DIP24,.3针数：24
Reach Compliance Code：not_compliantECCN代码：3A001.A.2.C
HTS代码：8542.39.00.01风险等级：5.1
最大模拟输入电压：10 V最小模拟输入电压：-10 V
最长转换时间：9 µs转换器类型：ADC, SUCCESSIVE APPROXIMATION
JESD-30 代码：R-CDIP-T24JESD-609代码：e0
最大线性误差 (EL)：0.0244%标称负供电电压：-5 V
模拟输入通道数量：1位数：12
功能数量：1端子数量：24
最高工作温度：125 °C最低工作温度：-55 °C
输出位码：BINARY输出格式：SERIAL, PARALLEL, 8 BITS, PARALLEL, WORD
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：DIP
封装等效代码：DIP24,.3封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT APPLICABLE
电源：+-5 V认证状态：Qualified
采样并保持/跟踪并保持：TRACK筛选级别：MIL-STD-883
子类别：Analog to Digital Converters标称供电电压：5 V
表面贴装：NO技术：CMOS
温度等级：MILITARY端子面层：Tin/Lead (Sn63Pb37)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT APPLICABLE
Base Number Matches：1

5962-9317901MLA 数据手册

 浏览型号5962-9317901MLA的Datasheet PDF文件第5页浏览型号5962-9317901MLA的Datasheet PDF文件第6页浏览型号5962-9317901MLA的Datasheet PDF文件第7页浏览型号5962-9317901MLA的Datasheet PDF文件第9页浏览型号5962-9317901MLA的Datasheet PDF文件第10页浏览型号5962-9317901MLA的Datasheet PDF文件第11页 
AD7870/AD7875/AD7876  
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS  
RD  
BUSY/INT  
CLK  
1
2
3
4
5
6
7
8
9
24 CS  
23 CONVST  
22 12/8/CLK  
AD7870/  
AD7875/  
AD7876  
4
3
2
1
28 27 26  
DB11/HBEN  
DB10/SSTRB  
DB9/SCLK  
DB8/SDATA  
DB7/LOW  
DB6/LOW  
21  
20  
V
V
SS  
IN  
PIN 1  
INDENTFIER  
5
6
25  
24  
23  
22  
21  
20  
DB11/HBEN  
DB10/SSTRB  
DB9/SCLK  
NC  
V
V
SS  
19 REF OUT  
18 AGND  
TOP VIEW  
(Not to Scale)  
IN  
7
AD7870/AD7875/  
AD7876  
REF OUT  
NC  
17  
V
DD  
8
16 DB0/DB8  
15 DB1/DB9  
14 DB2/DB10  
13 DB3/DB11  
DB5/LOW 10  
DB4/LOW 11  
DGND 12  
DB8/SDATA  
DB7/LOW  
9
TOP VIEW  
AGND  
(Not to Scale)  
10  
V
DD  
DB6/LOW 11  
19 DB0/DB8  
12 13 14 15 16 17 18  
NC = NO CONNECT  
Figure 3. PLCC Pin Configuration  
Figure 2. DIP and SOIC Pin Configuration  
Table 5. Pin Function Descriptions  
DIP and SOIC PLCC  
Pin No.  
Pin No.  
Mnemonic  
Function  
NꢀA  
1, 8, 15,  
22  
NC  
No Connect.  
1
2
2
3
RD  
CS  
Read. Active low logic input. This input is used in conjunction with low to enable the data outputs.  
BUSY INT  
ꢀ
BusyꢀInterrupt. Active low logic output indicating converter status. See Figure 1/, Figure 15, Figure 16,  
and Figure 17.  
3
/
/
5
CLK  
Clock Input. An external TTL-compatible clock may be applied to this input pin. Alternatively, tying this  
pin to VSS enables the internal laser-trimmed clock oscillator.  
DB11ꢀHBEN  
8
Data Bit 11 (MSB)ꢀHigh Byte Enable. The function of this pin is dependent on the state of the 12ꢀ ꢀCLK  
input. When 12-bit parallel data is selected, this pin provides the DB11 output. When byte data is  
selected, this pin becomes the HBEN logic input. HBEN is used for 8-bit bus interfacing. When HBEN is  
low, DB7ꢀLOW to DB0ꢀDB8 become DB7 to DB0. With HBEN high, DB7ꢀLOW to DB0ꢀDB8 are used for  
the upper byte of data (see Table 6).  
5
6
6
7
SSTRB  
DB10ꢀ  
Data Bit 10ꢀSerial Strobe. When 12-bit parallel data is selected, this pin provides the DB10 output.  
SSTRB  
is an active low open-drain output that provides a strobe or framing pulse for serial data. An  
SSTRB  
external /.7 kΩ pull-up resistor is required on  
.
DB9ꢀSCLK  
Data Bit 9ꢀSerial Clock. When 12-bit parallel data is selected, this pin provides the DB9 output. SCLK is  
8
the gated serial clock output derived from the internal or external ADC clock. If the 12ꢀ ꢀCLK input is at  
8
−5 V, then SCLK runs continuously. If 12ꢀ ꢀCLK is at 0 V, then SCLK is gated off after serial transmission is  
complete. SCLK is an open-drain output and requires an external 2 kΩ pull-up resistor.  
7
9
DB8ꢀSDATA  
Data Bit 8ꢀSerial Data. When 12-bit parallel data is selected, this pin provides the DB8 output. SDATA is  
SSTRB  
an open-drain serial data output which is used with SCLK and  
for serial data transfer. Serial data  
SSTRB  
is valid on the falling edge of SCLK while  
SDATA.  
is low. An external /.7 kΩ pull-up resistor is required on  
8 to11  
10 to 13  
DB7ꢀLOW–  
DB/ꢀLOW  
CS  
RD  
8
Three-state data outputs controlled by and . Their function depends on the 12ꢀ ꢀCLK and HBEN  
8
8
inputs. With 12ꢀ ꢀCLK high, they are always DB7–DB/. With 12ꢀ ꢀCLK low or −5 V, their function is  
controlled by HBEN (see Table 6).  
12  
1/  
DGND  
Digital Ground. Ground reference for digital circuitry.  
13 to 16  
16 to 19  
DB3ꢀDB11–  
DB0ꢀDB8  
CS  
RD  
8
Three-state data outputs which are controlled by and . Their function depends on the 12ꢀ ꢀCLK  
8
8
and HBEN inputs. With 12ꢀ ꢀCLK high, they are always DB3–DB0. With 12ꢀ ꢀCLK low or −5 V, their  
function is controlled by HBEN (see Table 6).  
17  
20  
VDD  
Positive Supply, +5 V 5ꢁ.  
Rev. C | Page 8 of 28  
 
1...567891011...28

中文翻译

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5962-9317901MLA 替代型号

型号 品牌 替代类型 描述 数据表
AD7876TQ ADI

类似代替

 LC2MOS Complete, 12-Bit, 100 kHz, Sampling ADCs
AD7876CN ADI

完全替代

 LC2MOS Complete, 12-Bit, 100 kHz, Sampling ADCs
AD7876BQ ADI

完全替代

 LC2MOS Complete, 12-Bit, 100 kHz, Sampling ADCs

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