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5962-8684602VA PDF预览

5962-8684602VA

更新时间： 2024-11-29 14:51:03
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
8页 76K
描述
CDIP-18, Tube

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5962-8684602VA 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：CDIP
包装说明：DIP, DIP18,.3针数：18
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.32.00.71风险等级：5.91
Is Samacsys：N最长访问时间：40 ns
最大时钟频率 (fCLK)：15 MHz周期时间：66.67 ns
JESD-30 代码：R-GDIP-T18JESD-609代码：e0
长度：22.987 mm内存密度：320 bit
内存集成电路类型：OTHER FIFO内存宽度：5
湿度敏感等级：1功能数量：1
端子数量：18字数：64 words
字数代码：64工作模式：ASYNCHRONOUS
最高工作温度：125 °C最低工作温度：-55 °C
组织：64X5输出特性：3-STATE
可输出：YES封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装等效代码：DIP18,.3
封装形状：RECTANGULAR封装形式：IN-LINE
并行/串行：PARALLEL峰值回流温度（摄氏度）：240
电源：5 V认证状态：Not Qualified
筛选级别：38535Q/M;38534H;883B座面最大高度：5.08 mm
最大待机电流：0.09 A子类别：FIFOs
最大压摆率：0.09 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.62 mmBase Number Matches：1

5962-8684602VA 数据手册

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IDT72401  
IDT72402  
IDT72403  
IDT72404  
CMOS PARALLEL FIFO  
64 x 4 and 64 x 5  
Integrated Device Technology, Inc.  
64 words by 5 bits. The IDT72403 and IDT72404 also have an  
Output Enable (OE) pin. The FlFOs accept 4-bit or 5-bit data  
at the data input (D0-D3, 4). The stored data stack up on a first-  
in/first-out basis.  
FEATURES:  
• First-ln/First-Out Dual-Port memory  
• 64 x 4 organization (IDT72401/72403)  
• 64 x 5 organization (IDT72402/72404)  
• RAM-based FIFO with low falI-through time  
• Low-power consumption  
— Active: 175mW (typ.)  
• Maximum shift rate — 45MHz  
• High data output drive capability  
• Asynchronous and simultaneous read and write  
• Fully expandable by bit width  
A Shift Out (SO) signal causes the data at the next to last  
word to be shifted to the output while all other data shifts down  
one location in the stack. The Input Ready (IR) signal acts like  
a flag to indicate when the input is ready for new data  
(IR = HIGH) or to signal when the FIFO is full (IR = LOW). The  
IR signal can also be used to cascade multiple devices  
together. The Output Ready (OR) signal is a flag to indicate  
that the output remains valid data (OR = HIGH) or to indicate  
that the FIFO is empty (OR = LOW). The OR can also be used  
to cascade multiple devices together.  
• Fully expandable by word depth  
• IDT72403/72404 have Output Enable pin to enable  
output data  
Width expansion is accomplished by logically ANDing the  
IR and OR signals to form composite signals.  
• High-speed data communications applications  
• High-performance CMOS technology  
• Available in CERDIP, plastic DIP and SOIC  
• Military product compliant to MlL-STD-883, Class B  
• Standard Military Drawing #5962-86846 and  
5962-89523 is listed on this function.  
• Industrial temperature range (–40°C to +85°C) is avail-  
able (plastic packages only)  
Depth expansion is accomplished by tying the data inputs  
of one device to the data outputs of the previous device. The  
IR pin of the receiving device is connected to the SO pin of the  
sending device and the OR pin of the sending device is  
connected to the Shift In (SI) pin of the receiving device.  
Reading and writing operations are completely asynchro-  
nous allowing the FIFO to be used as a buffer between two  
digital machines of widely varying operating frequencies. The  
45MHz speed makes these FlFOs ideal for high-speed com-  
munication and controller applications.  
DESCRIPTION:  
The IDT72401 and IDT72403 are asynchronous high-  
performance First-ln/First-Out memories organized 64 words  
by 4 bits. The IDT72402 and IDT72404 are asynchronous  
high-performance First-ln/First-Out memories organized as  
Military grade product is manufactured in compliance with  
the latest revision of MIL-STD-883, Class B.  
FUNCTIONAL BLOCK DIAGRAM  
OUTPUT  
ENABLE  
INPUT  
CONTROL  
LOGIC  
OE (IDT72403 and  
IDT72404)  
SI  
IR  
WRITE POINTER  
WRITE MULTIPLEXER  
D0-3  
D4  
(IDT72402  
and IDT72404)  
Q0-3  
MEMORY  
ARRAY  
DATAIN  
DATAOUT  
Q
4
(IDT72402 and  
IDT72404)  
READ MULTIPLEXER  
READ POINTER  
MASTER  
RESET  
SO  
OR  
MR  
OUTPUT  
CONTROL  
LOGIC  
2747 drw 01  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
FAST is a trademark of National Semiconductor, Inc.  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
MAY 1998  
©1998 Integrated Device Technology, Inc.  
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.  
DSC-2747/7  
1
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