Datasheet > 552JH1213M000DGR

552JH1213M000DGR

更新时间： 2024-11-08 10:26:23

品牌	Logo	应用领域
芯科 - SILICON		/
页数	文件大小	规格书
14页	236K
描述
Oscillator

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数据手册

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552JH1213M000DGR 数据手册

Si552

REVISION D

DUAL FREQUENCY VOLTAGE-CONTROLLED CRYSTAL

OSCILLATOR (VCXO) 10 MHZ TO 1.4 GHZ

Features

ꢀ

Available with any-rate output

frequencies from 10–945 MHz and

selected frequencies to 1.4 GHz

ꢀ

Internal fixed crystal frequency

ensures high reliability and low

aging

Si5602

ꢀ

Two selectable output frequencies ꢀ Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

3rd generation DSPLL with superior

ꢀ

jitter performance

ꢀ

3x better frequency stability than

SAW-based oscillators

ꢀ

Pb-free/RoHS-compliant

Ordering Information:

Applications

See page 8.

ꢀ

SONET/SDH

xDSL

10 GbE LAN/WAN

ꢀ

Low-jitter clock generation

Optical modules

Clock and data recovery

Pin Assignments:

See page 7.

Description

The Si552 dual-frequency VCXO utilizes Silicon Laboratories’ advanced

DSPLL circuitry to provide a very low jitter clock for all output frequencies.

(Top View)

The Si552 is available with any-rate output frequency from 10 to 945 MHz

and selected frequencies to 1400 MHz. Unlike traditional VCXOs, where a

different crystal is required for each output frequency, the Si552 uses one

fixed crystal frequency to provide a wide range of output frequencies. This

IC-based approach allows the crystal resonator to provide exceptional

frequency stability and reliability. In addition, DSPLL clock synthesis

provides superior supply noise rejection, simplifying the task of generating

low-jitter clocks in noisy environments typically found in communication

systems. The Si552 IC-based VCXO is factory-configurable for a wide

variety of user specifications including frequency, supply voltage, output

format, tuning slope, and temperature stability. Specific configurations are

factory programmed at time of shipment, thereby eliminating the long lead

times associated with custom oscillators.

V_C

V_DD

CLK–

CLK+

GND

Functional Block Diagram

V_DD

CLK-

CLK+

Any-rate

10–1400 MHz

DSPLL^®

Fixed

Frequency XO

Clock Synthesis

ADC

V_C

GND

Rev. 0.6 6/07

Si552

12 3 4 5 6 7...14

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