Si552
DUAL FREQUENCY VCXO (10 MHZ TO 1.4 GHZ)
Features
ꢀ
Available with any-rate output
frequencies from 10–945 MHz and
select frequencies to 1.4 GHz
ꢀ
Internal fixed crystal frequency
ensures high reliability and low
aging
Si5602
ꢀ
ꢀ
Two selectable output frequencies ꢀ Available CMOS, LVPECL, LVDS
®
& CML outputs
3rd generation DSPLL with superior
jitter performance
ꢀ
ꢀ
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
ꢀ
3x better frequency stability than
SAW-based oscillators
ꢀ
Pb-free/RoHS-compliant
Ordering Information:
Applications
See page 7.
ꢀ
ꢀ
ꢀ
SONET/SDH
xDSL
10 GbE LAN / WAN
ꢀ
ꢀ
ꢀ
Low-jitter clock generation
Optical Modules
Clock and data recovery
Pin Assignments:
See page 6.
Description
The Si552 dual frequency VCXO utilizes Silicon Laboratories advanced
DSPLL circuitry to provide a very low jitter clock for all output frequencies.
(Top View)
®
The Si552 is available with any-rate output frequency from 10 to 945 MHz
and select frequencies to 1400 MHz. Unlike traditional VCXO’s where a
different crystal is required for each output frequency, the Si552 uses one
fixed crystal frequency to provide a wide range of output frequencies. This
IC based approach allows the crystal resonator to provide exceptional
frequency stability and reliability. In addition, DSPLL clock synthesis
provides superior supply noise rejection, simplifying the task of generating
low jitter clocks in noisy environments typically found in communication
systems. The Si552 IC based VCXO is factory configurable for a wide
variety of user specifications including frequency, supply voltage, output
format, tuning slope, and temperature stability. Specific configurations are
factory programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
VC
VDD
1
2
3
6
5
4
FS
CLK–
CLK+
GND
Functional Block Diagram
VDD
CLK-
CLK+
Any-rate
10–1400 MHz
DSPLL®
Fixed
Frequency XO
Clock Synthesis
ADC
FS
VC
GND
Rev. 0.5 7/06
Copyright © 2006 by Silicon Laboratories
Si552