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550AF100M000BGR PDF预览

550AF100M000BGR

更新时间: 2024-12-01 14:47:51
品牌 Logo 应用领域
芯科 - SILICON 机械输出元件振荡器
页数 文件大小 规格书
12页 207K
描述
LVCMOS Output Clock Oscillator, 100MHz Nom, ROHS COMPLIANT PACKAGE-6

550AF100M000BGR 技术参数

生命周期:ObsoleteReach Compliance Code:unknown
风险等级:5.6其他特性:COMPLEMENTARY OUTPUT; TRI-STATE; ENABLE/DISABLE FUNCTION; TAPE AND REEL
最大控制电压:3.3 V最小控制电压:
最长下降时间:0.35 ns频率调整-机械:NO
频率偏移/牵引率:100 ppm频率稳定性:50%
线性度:10%安装特点:SURFACE MOUNT
标称工作频率:100 MHz最高工作温度:85 °C
最低工作温度:-40 °C振荡器类型:LVCMOS
物理尺寸:7.0mm x 5.0mm x 1.85mm最长上升时间:0.35 ns
最大供电电压:3.63 V最小供电电压:2.97 V
标称供电电压:3.3 V表面贴装:YES
最大对称度:55/45 %Base Number Matches:1

550AF100M000BGR 数据手册

 浏览型号550AF100M000BGR的Datasheet PDF文件第2页浏览型号550AF100M000BGR的Datasheet PDF文件第3页浏览型号550AF100M000BGR的Datasheet PDF文件第4页浏览型号550AF100M000BGR的Datasheet PDF文件第5页浏览型号550AF100M000BGR的Datasheet PDF文件第6页浏览型号550AF100M000BGR的Datasheet PDF文件第7页 
Si550  
PRELIMINARY DATA SHEET  
VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR (VCXO)  
10 MHZ TO 1.4 GHZ  
Features  
Available with any-rate output Internal fixed crystal frequency  
Si5602  
frequencies from 10 MHz to  
945 MHz and selected frequencies  
to 1.4 GHz  
ensures high reliability and low  
aging  
Available CMOS, LVPECL,  
LVDS, & CML outputs  
3.3, 2.5, and 1.8 V supply options  
Industry-standard 5 x 7 mm  
package and pinout  
®
3rd generation DSPLL with  
superior jitter performance  
3x better frequency stability than  
SAW based oscillators  
Lead-free/RoHS-compliant  
Ordering Information:  
Applications  
See page 8.  
SONET / SDH  
xDSL  
10 GbE LAN / WAN  
Low-jitter clock generation  
Optical modules  
Clock and data recovery  
Pin Assignments:  
See page 7.  
Description  
(Top View)  
®
The Si550 VCXO utilizes Silicon Laboratories’ advanced DSPLL circuitry to  
provide a low-jitter clock at high frequencies. The Si550 is available with  
any-rate output frequency from 10 to 945 MHz and selected frequencies to  
1400 MHz. Unlike traditional VCXO’s where a different crystal is required for  
each output frequency, the Si550 uses one fixed crystal to provide a wide  
range of output frequencies. This IC based approach allows the crystal  
resonator to provide exceptional frequency stability and reliability. In  
addition, DSPLL clock synthesis provides superior supply noise rejection,  
simplifying the task of generating low-jitter clocks in noisy environments  
typically found in communication systems. The Si550 IC-based VCXO is  
factory configurable for a wide variety of user specifications, including  
frequency, supply voltage, output format, tuning slope, and temperature  
stability. Specific configurations are factory programmed at time of shipment,  
thereby eliminating long lead times associated with custom oscillators.  
VC  
VDD  
1
2
3
6
5
4
OE  
CLK–  
CLK+  
GND  
Functional Block Diagram  
CLK– CLK+  
VDD  
Any-rate  
10-1400 MHz  
DSPLL®  
Fixed  
Frequency  
XO  
Clock Synthesis  
ADC  
Vc  
OE  
GND  
Preliminary Rev. 0.3 4/06  
Copyright © 2006 by Silicon Laboratories  
Si550  
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.  

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