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550AF1213M000DG PDF预览

550AF1213M000DG

更新时间: 2024-12-01 17:23:19
品牌 Logo 应用领域
芯科 - SILICON 石英晶振压控振荡器
页数 文件大小 规格书
14页 231K
描述
VCXO, Clock, 10MHz Min, 1417MHz Max, 1213MHz Nom

550AF1213M000DG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active包装说明:DILCC6,.25
Reach Compliance Code:unknown风险等级:5.62
JESD-609代码:e3安装特点:SURFACE MOUNT
端子数量:6最大工作频率:1417 MHz
最小工作频率:10 MHz标称工作频率:1213 MHz
最高工作温度:85 °C最低工作温度:-40 °C
最大输出低电流:32 mA封装主体材料:PLASTIC/EPOXY
封装等效代码:DILCC6,.25电源:3.3 V
认证状态:Not Qualified子类别:Other Oscillators
最大压摆率:130 mA标称供电电压:3.3 V
表面贴装:YES端子面层:Matte Tin (Sn)
Base Number Matches:1

550AF1213M000DG 数据手册

 浏览型号550AF1213M000DG的Datasheet PDF文件第2页浏览型号550AF1213M000DG的Datasheet PDF文件第3页浏览型号550AF1213M000DG的Datasheet PDF文件第4页浏览型号550AF1213M000DG的Datasheet PDF文件第5页浏览型号550AF1213M000DG的Datasheet PDF文件第6页浏览型号550AF1213M000DG的Datasheet PDF文件第7页 
Si550  
REVISION D  
VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR (VCXO)  
10 MHZ TO 1.4 GHZ  
Features  
Available with any-rate output Internal fixed crystal frequency  
Si5602  
frequencies from 10 to 945 MHz  
and selected frequencies to  
1.4 GHz  
ensures high reliability and low  
aging  
Available CMOS, LVPECL,  
LVDS, and CML outputs  
3.3, 2.5, and 1.8 V supply options  
Industry-standard 5 x 7 mm  
package and pinout  
®
3rd generation DSPLL with  
superior jitter performance  
3x better frequency stability than  
SAW-based oscillators  
Lead-free/RoHS-compliant  
Ordering Information:  
Applications  
See page 8.  
SONET/SDH  
xDSL  
10 GbE LAN/WAN  
Low-jitter clock generation  
Optical modules  
Clock and data recovery  
Pin Assignments:  
See page 7.  
Description  
(Top View)  
®
The Si550 VCXO utilizes Silicon Laboratories’ advanced DSPLL circuitry to  
provide a low-jitter clock at high frequencies. The Si550 is available with  
any-rate output frequency from 10 to 945 MHz and selected frequencies to  
1400 MHz. Unlike traditional VCXOs, where a different crystal is required for  
each output frequency, the Si550 uses one fixed crystal to provide a wide  
range of output frequencies. This IC-based approach allows the crystal  
resonator to provide exceptional frequency stability and reliability. In  
addition, DSPLL clock synthesis provides superior supply noise rejection,  
simplifying the task of generating low-jitter clocks in noisy environments  
typically found in communication systems. The Si550 IC-based VCXO is  
factory-configurable for a wide variety of user specifications, including  
frequency, supply voltage, output format, tuning slope, and temperature  
stability. Specific configurations are factory programmed at time of shipment,  
thereby eliminating the long lead times associated with custom oscillators.  
VC  
VDD  
1
2
3
6
5
4
OE  
CLK–  
CLK+  
GND  
Functional Block Diagram  
CLK– CLK+  
VDD  
Any-rate  
10-1400 MHz  
DSPLL®  
Fixed  
Frequency  
XO  
Clock Synthesis  
ADC  
Vc  
OE  
GND  
Rev. 0.6 6/07  
Copyright © 2007 by Silicon Laboratories  
Si550  

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