™
Ultra Series Crystal Oscillator
Si540 Data Sheet
Ultra Low Jitter Any-Frequency XO (125 fs), 0.2 to 1500 MHz
KEY FEATURES
The Si540 Ultra Series™ oscillator utilizes Silicon Laboratories’ advanced 4th
generation DSPLL® technology to provide an ultra-low jitter, low phase noise clock
at any output frequency. The device is factory-programmed to any frequency from
0.2 to 1500 MHz with <1 ppb resolution and maintains exceptionally low jitter for
both integer and fractional frequencies across its operating range. The Si540
offers excellent reliability and frequency stability as well as guaranteed aging
performance. On-chip power supply filtering provides industry-leading power
supply noise rejection, simplifying the task of generating low jitter clocks in noisy
systems that use switched-mode power supplies. Offered in industry-standard
3.2×5 mm and 5×7 mmfootprints, the Si540 has a dramatically simplified supply
chain that enables Silicon Labs to ship custom frequency samples 1-2 weeks after
receipt of order. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si540 uses one simple crystal and a DSPLL IC-based
approach to provide the desired output frequency. This process also guarantees
100% electrical testing of every device. The Si540 is factory-configurable for a
wide variety of user specifications, including frequency, output format, and OE pin
location/polarity. Specific configurations are factory-programmed at time of
shipment, eliminating the long lead times associated with custom oscillators.
• Available with any frequency from 0.2 MHz to
1500 MHz
• Very low jitter: 125 fs Typ RMS
(12 kHz – 20 MHz)
• Excellent PSRR and supply noise immunity:
–80 dBc Typ
• 7 ppm stability option (-40 to 85C)
• 3.3 V, 2.5 V and 1.8 V V supply operation
DD
from the same part number
• LVPECL, LVDS, CML, HCSL, CMOS, and
Dual CMOS output options
• 3.2×5, 5x7 mm package footprints
• Any custom frequency available with 1-2
week lead times
APPLICATIONS
• 100G/200G/400G OTN, coherent optics
• 10G/40G/100G optical ethernet
Pin Assignments
• 3G-SDI/12G-SDI/24G-SDI broadcast video
1
2
3
6
5
4
VDD
CLK-
CLK+
OE/NC
NC/OE
GND
• Servers, switches, storage, NICs, search
acceleration
• Test and measurement
• Clock and data recovery
• FPGA/ASIC clocking
(Top View)
Fixed
Frequency
Crystal
Frequency
Flexible
DSPLL
Pin #
Descriptions
Low
Noise
1, 2
Selectable via ordering option
OE = Output enable; NC = No connect
Driver
DCO
Digital
Phase
Detector
Digital
Phase Error
Loop
OSC
Cancellation
Filter
3
4
5
GND = Ground
Flexible
Formats,
1.8V – 3.3V
Phase Error
CLK+ = Clock output
Fractional
Operation
Divider
NVM
Control
CLK- = Complementary clock output. Not used
for CMOS.
Power Supply Regulation
6
VDD = Power supply
Output Enable
(Pin Control)
Built-in Power Supply
Noise Rejection
silabs.com | Building a more connected world.
Rev. 1.0
5秒后页面跳转
全球首块英伟达H200交付 黄仁勋“送货上门”
常用8脚开关电源芯片型号大全
74HC04芯片引脚图及功能、应用电路图讲解
CR6842芯片参数、引脚配置、应用电路图详解
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
