Datasheet > 540BBA775M000ABGR

540BBA775M000ABGR

更新时间： 2023-02-15 00:00:00

品牌	Logo	应用领域
芯科 - SILICON		/
页数	文件大小	规格书
16页	834K
描述
LVDS Output Clock Oscillator,

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540BBA775M000ABGR 数据手册

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Si540 Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition/Comment

Mid-level (2.5 V, 3.3 V VDD)

Mid-level (1.8 V VDD)

Swing (diff)

Min

1.125

0.8

Typ

1.20

0.9

0.7

750

Max

1.275

1.0

Unit

LVDS Output Option⁴

V_OC

V_O

V_OH

V_OL

V_C

0.5

0.9

V_PP

HCSL Output Option⁵

Output voltage high

Output voltage low

Crossing voltage

660

–150

250

0.6

850

150

350

0.8

—

550

CML Output Option (AC-Coupled)

CMOS Output Option

V_O

Swing (diff)

1.0

V_OH

V_OL

I_OH= 8/6/4 mA for 3.3/2.5/1.8V VDD 0.85 × V_DD

I_OL= 8/6/4 mA for 3.3/2.5/1.8V VDD

—

0.15 × V_DD

Notes:

1. Total Stability includes temperature stability, initial accuracy, load pulling, VDD variation, and aging for 20 yrs at 70 ºC.

2. OE includes a 50 kΩ pull-up to VDD for OE active high. Includes a 50 kΩ pull-down to GND for OE active low. NC (No Connect)

pins include a 50 kΩ pull-down to GND.

3. 50 Ω to V_DD– 2.0 V.

4. R_term= 100 Ω (differential).

5. 50 Ω to GND.

Table 2.2. Clock Output Phase Jitter and PSRR

V_DD= 1.8 V, 2.5 or 3.3 V ± 5%, T_A= –40 to 85 ºC

Parameter

Symbol

Test Condition/Comment

Differential Formats

CMOS, Dual CMOS

Differential Formats

CMOS, Dual CMOS

100 kHz sine wave

200 kHz sine wave

500 kHz sine wave

1 MHz sine wave

Min

—

Typ

125

200

150

200

-83

-82

-85

Max

200

—

Unit

Phase Jitter (RMS, 12kHz - 20MHz)¹

3.2 x 5 mm, F_CLK≥ 100 MHz

ϕ_J

Phase Jitter (RMS, 12kHz - 20MHz)¹

5 x 7 mm, F_CLK≥ 100 MHz

200

—

Spurs Induced by External Power Supply

Noise, 50 mVpp Ripple. LVDS 156.25 MHz

Output

PSRR

—

dBc

—

Note:

1. Guaranteed by characterization. Jitter inclusive of any spurs.

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