3N166
P-CHANNEL MOSFET
The 3N166 is a monolithic dual enhancement mode P-Channel Mosfet
FEATURES
The 3N166 is a dual enhancement mode P-Channel
Mosfet and is ideal for space constrained applications
and those requiring tight electrical matching.
DIRECT REPLACEMENT FOR INTERSIL 3N166
ABSOLUTE MAXIMUM RATINGS1@ 25°C (unless otherwise noted)
Maximum Temperatures
The hermetically sealed TO-78 package is well suited
for high reliability and harsh environment applications.
Storage Temperature
‐65°C to +200°C
‐55°C to +150°C
Operating Junction Temperature
Lead Temperature (Soldering, 10 sec.)
Maximum Power Dissipation
Continuous Power Dissipation (one side)
Total Derating above 25°C
MAXIMUM CURRENT
+300°C
(See Packaging Information).
300mW
4.2 mW/°C
3N166 Features:
Very high Input Impedance
Low Capacitance
High Gain
High Gate Breakdown Voltage
Low Threshold Voltage
Drain Current
50mA
MAXIMUM VOLTAGES
Drain to Gate or Drain to Source2
‐30V
±125V
±80V
Peak Gate to Source3
Gate‐Gate Voltage
3N166 ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)
SYMBOL
IGSSR
IGSSF
CHARACTERISTIC
Gate Reverse Leakage Current
Gate Forward Current
MIN
‐‐
‐‐
TYP.
‐‐
‐‐
MAX
10
‐10
UNITS
pA
CONDITIONS
GS = ‐0V
VGS = ‐40V
V
TA= +125°C
‐‐
‐‐
‐25
IDSS
ISDS
ID(on)
VGS(th)
Drain to Source Leakage Current
Source to Drain Leakage Current
Drain Current “On”
‐‐
‐‐
‐5.0
‐2.0
‐2.0
‐‐
‐‐
‐‐
‐‐
‐‐
‐‐
‐‐
‐‐
‐200
‐400
‐30
‐5.0
‐5.0
300
3000
VDS = ‐20V
VSD = ‐20V VDB = 0
mA
V
VDS = ‐15V, VGS = ‐10V
VDS = ‐15V, ID = ‐10µA
VDS = VGS , ID = ‐10µA
VGS = ‐20V, ID = ‐100µA
VDS = ‐15V, ID = ‐10mA , f = 1kHz
Gate to Source Threshold Voltage
rDS(on)
gfs
Drain to Source “On” Resistance
Forward Transconductance
Ω
µS
1500
gos
Output Admittance
‐‐
‐‐
300
Ciss
Crss
Input Capacitance
Reverse Transfer Capacitance
‐‐
‐‐
‐‐
‐‐
3
0.7
pF
VDS = ‐15V, ID = ‐10mA , f = 1MHz4
Click To Buy
Coss
RE(Yfs)
Output Capacitance
Common Source Forward
Transconductance
‐‐
1200
‐‐
‐‐
3.0
‐‐
µS
VDS = ‐15V, ID = ‐10mA , f = 100MHz4
MATCHING CHARACTERISTICS 3N166
SYMBOL
CHARACTERISTIC
Forward Transconductance Ratio
Gate Source Threshold Voltage
Differential
LIMITS
UNITS
ns
mV
CONDITIONS
MIN
0.90
‐‐
MAX
1.0
100
Yfs1/Yfs2
VGS1‐2
VDS = ‐15V, ID = ‐500µA , f = MHz4
VDS = ‐15V, ID = ‐500µA
∆VGS1‐2/∆T
Gate Source Threshold Voltage
Differential Change with Temperature
‐‐
100
µV/°C
VDS = ‐15V, ID = ‐500µA
TA = ‐55°C to = +25°C
SWITCHING TEST CIRCUIT
Note 1 ‐ Absolute maximum ratings are limiting values above which 3N166 serviceability may be impaired. *
Note 2 – Per Transistor
SWITCHING WAVEFORM & TEST CIRCUIT
Note 3 – Device must not be tested at ±125V more than once or longer than 300ms.
Note 4 – For design reference only, not 100% tested
Available Packages:
Device Schematic
TO-78 (Bottom View)
3N166 in TO-72
3N166 in bare die.
Please contact Micross for full
package and die dimensions
*To avoid possible damage to the device while wiring, testing, or in actual
operation, follow these procedures: To avoid the build‐up of static charge, the
leads of the devices should remain shorted together with a metal ring except
when being tested or used. Avoid unnecessary handling. Pick up devices by the
case instead of the leads. Do not insert or remove devices from circuits with the
power on, as transient voltages may cause permanant damage to the devices.
Tel: +44 1603 788967
Email: chipcomponents@micross.com
Web: http://www.micross.com/distribution
Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or
other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.
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