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3D3323K-6000 PDF预览

3D3323K-6000

更新时间： 2024-11-21 03:47:07
品牌 Logo 应用领域
DATADELAY 延迟线
页数 文件大小 规格书
4页 243K
描述
MONOLITHIC TRIPLE FIXED DELAY LINE

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3D3323K-6000 数据手册

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3D3323  
MONOLITHIC TRIPLE  
FIXED DELAY LINE  
(SERIES 3D3323)  
FEATURES  
PACKAGES  
•
•
•
•
•
•
•
•
•
•
All-silicon, low-power CMOS technology  
Vapor phase, IR and wave solderable  
Auto-insertable (DIP pkg.)  
I1  
I2  
I3  
VDD  
O1  
O2  
I1  
N/C  
I2  
N/C  
I3  
VDD  
N/C  
O1  
N/C  
O2  
N/C  
O3  
1
2
3
4
8
7
6
5
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
Low ground bounce noise  
GND  
O3  
Leading- and trailing-edge accuracy  
Delay range: 10 through 6000ns  
Delay tolerance: 2% or 1.0ns  
Temperature stability: ±3% typ (-40C to 85C)  
Vdd stability: ±1% typical (3.0V to 3.6V)  
Minimum input pulse width: 20% of total  
delay  
3D3323M DIP  
3D3323H Gull-Wing  
N/C  
GND  
I1  
I2  
1
2
3
4
8
7
6
5
VDD  
O1  
8
I3  
O2  
3D3323 DIP  
GND  
O3  
3D3323G Gull-Wing  
3D3323K Unused pins  
removed  
3D3323Z SOIC  
(150 Mil)  
•
•
14-pin DIP available as drop-in replacement for  
hybrid delay lines  
For mechanical dimensions, click here.  
For package marking details, click here.  
FUNCTIONAL DESCRIPTION  
PIN DESCRIPTIONS  
The 3D3323 Triple Delay Line product family consists of fixed-delay  
CMOS integrated circuits. Each package contains three matched,  
independent delay lines. Delay values can range from 10ns through  
6000ns. The input is reproduced at the output without inversion,  
shifted in time as per the user-specified dash number. The 3D3323  
is CMOS-compatible and features both rising- and falling-edge  
accuracy.  
I1  
Delay Line 1 Input  
Delay Line 2 Input  
Delay Line 3 Input  
Delay Line 1 Output  
Delay Line 2 Output  
Delay Line 3 Output  
I2  
I3  
O1  
O2  
O3  
VDD +3.3 Volts  
GND Ground  
The all-CMOS 3D3323 integrated circuit has been designed as a  
reliable, economic alternative to hybrid fixed delay lines. It is offered  
N/C  
No Connection  
in a standard 8-pin auto-insertable DIP and a space saving surface mount 8-pin SOIC.  
TABLE 1: PART NUMBER SPECIFICATIONS  
PART NUMBER  
DELAY  
PER LINE  
(ns)  
INPUT RESTRICTIONS  
DIP-8  
SOIC-8  
DIP-14  
3D3323  
3D3323G  
-10  
DIP-14  
Max Operating Absolute Max  
Min Operating  
Absolute Min  
Oper. P.W.  
3D3323M 3D3323Z  
3D3323H  
3D3323K  
Frequency  
Oper. Freq.  
Pulse Width  
-10  
-15  
-10  
-15  
-10  
-15  
33.3 MHz  
22.2 MHz  
16.7 MHz  
13.3 MHz  
11.1 MHz  
8.33 MHz  
6.67 MHz  
3.33 MHz  
1.67 MHz  
0.67 MHz  
0.33 MHz  
0.05 MHz  
100.0 MHz  
100.0 MHz  
100.0 MHz  
83.3 MHz  
71.4 MHz  
62.5 MHz  
50.0 MHz  
25.0 MHz  
12.5 MHz  
5.00 MHz  
2.50 MHz  
0.42 MHz  
15.0 ns  
22.5 ns  
5.0 ns  
5.0 ns  
10 ± 1.0  
15 ± 1.0  
-15  
-20  
-20  
-20  
-20  
30.0 ns  
5.0 ns  
20 ± 1.0  
-25  
-25  
-25  
-25  
37.5 ns  
6.0 ns  
25 ± 1.0  
-30  
-30  
-30  
-30  
45.0 ns  
7.0 ns  
30 ± 1.0  
-40  
-40  
-40  
-40  
60.0 ns  
8.0 ns  
40 ± 1.0  
-50  
-50  
-50  
-50  
75.0 ns  
10.0 ns  
20.0 ns  
40.0 ns  
100.0 ns  
200.0 ns  
1200.0 ns  
50 ± 1.0  
-100  
-200  
-500  
-1000  
-6000  
-100  
-200  
-500  
-1000  
-6000  
-100  
-200  
-500  
-1000  
-6000  
-100  
-200  
-500  
-1000  
-6000  
150.0 ns  
300.0 ns  
750.0 ns  
1500.0 ns  
9000.0 ns  
100 ± 2.0  
200 ± 4.0  
500 ± 10.0  
1000 ± 20  
6000 ±120  
NOTE: Any delay between 10 and 6000 ns not shown is also available.  
2006 Data Delay Devices  
Doc #06017  
5/10/2006  
DATA DELAY DEVICES, INC.  
3 Mt. Prospect Ave. Clifton, NJ 07013  
1
1234

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