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3D3324-10

更新时间： 2024-11-21 03:57:47
品牌 Logo 应用领域
DATADELAY 延迟线
页数 文件大小 规格书
4页 245K
描述
MONOLITHIC QUADRUPLE FIXED DELAY LINE

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中文翻译

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3D3324-10 技术参数

生命周期：Obsolete包装说明：,
Reach Compliance Code：compliant风险等级：5.84
Base Number Matches：1

3D3324-10 数据手册

 浏览型号3D3324-10的Datasheet PDF文件第2页浏览型号3D3324-10的Datasheet PDF文件第3页浏览型号3D3324-10的Datasheet PDF文件第4页 
3D3324  
MONOLITHIC QUADRUPLE  
FIXED DELAY LINE  
(SERIES 3D3324)  
FEATURES  
PACKAGES  
•
•
•
•
•
•
•
•
•
•
•
All-silicon, low-power CMOS technology  
Vapor phase, IR and wave solderable  
Auto-insertable (DIP pkg.)  
I1  
N/C  
I2  
I3  
I4  
VDD  
N/C  
O1  
N/C  
O2  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
I1  
N/C  
I2  
1
2
3
4
5
6
7
14  
VDD  
N/C  
O1  
Low ground bounce noise  
13  
12  
11  
10  
9
Leading- and trailing-edge accuracy  
Delay range: 10 through 6000ns  
Delay tolerance: 2% or 1.0ns  
I3  
N/C  
O2  
I4  
N/C  
GND  
O3  
N/C  
GND  
O3  
O4  
8
O4  
Temperature stability: ±3% typ (-40C to 85C)  
Vdd stability: ±1% typical (3.0V to 3.6V)  
Minimum input pulse width: 20% of total delay  
14-pin Gull-Wing available as drop-in  
replacement for hybrid delay lines  
8
3D3324D-xx  
SOIC  
3D3324-xx  
DIP  
(150 Mil)  
3D3324G-xx Gull-Wing  
For mechanical dimensions, click here.  
For package marking details, click here.  
FUNCTIONAL DESCRIPTION  
PIN DESCRIPTIONS  
The 3D3324 Quadruple Delay Line product family consists of fixed-  
delay CMOS integrated circuits. Each package contains four matched,  
independent delay lines. Delay values can range from 10ns through  
6000ns. The input is reproduced at the output without inversion,  
shifted in time as per the user-specified dash number. The 3D3324 is  
CMOS-compatible and features both rising- and falling-edge accuracy.  
I1  
Delay Line 1 Input  
Delay Line 2 Input  
Delay Line 3 Input  
Delay Line 4 Input  
Delay Line 1 Output  
Delay Line 2 Output  
Delay Line 3 Output  
Delay Line 4 Output  
I2  
I3  
I4  
O1  
O2  
O3  
O4  
The all-CMOS 3D3324 integrated circuit has been designed as a  
reliable, economic alternative to hybrid fixed delay lines. It is offered in  
a standard 14-pin auto-insertable DIP and a space saving surface  
mount 14-pin SOIC.  
VDD +3.3 Volts  
GND Ground  
N/C  
No Connection  
TABLE 1: PART NUMBER SPECIFICATIONS  
PART NUMBER  
DELAY  
PER LINE  
(ns)  
INPUT RESTRICTIONS  
DIP-14  
3D3324  
-10  
DIP-14  
SOIC-14  
Max Operating Absolute Max  
Min Operating  
Absolute Min  
Oper. P.W.  
5.0 ns  
3D3324G 3D3324D  
Frequency  
33.3 MHz  
22.2 MHz  
16.7 MHz  
13.3 MHz  
11.1 MHz  
8.33 MHz  
6.67 MHz  
3.33 MHz  
1.67 MHz  
Oper. Freq.  
100.0 MHz  
100.0 MHz  
100.0 MHz  
83.3 MHz  
71.4 MHz  
62.5 MHz  
50.0 MHz  
25.0 MHz  
12.5 MHz  
0.67 MHz  
0.33 MHz  
0.05 MHz  
Pulse Width  
15.0 ns  
-10  
-15  
-10  
-15  
10 ± 1.0  
15 ± 1.0  
20 ± 1.0  
25 ± 1.0  
30 ± 1.0  
40 ± 1.0  
50 ± 1.0  
100 ± 2.0  
200 ± 4.0  
-500  
-15  
22.5 ns  
5.0 ns  
-20  
-20  
-20  
30.0 ns  
5.0 ns  
-25  
-25  
-25  
37.5 ns  
6.0 ns  
-30  
-30  
-30  
45.0 ns  
7.0 ns  
-40  
-40  
-40  
60.0 ns  
8.0 ns  
-50  
-50  
-50  
75.0 ns  
10.0 ns  
20.0 ns  
40.0 ns  
750.0 ns  
1500.0 ns  
9000.0 ns  
-100  
-200  
-500  
-1000  
-6000  
-100  
-200  
-500  
-1000  
-6000  
-100  
-200  
-500  
-1000  
-6000  
150.0 ns  
300.0 ns  
5.00 MHz  
2.50 MHz  
0.42 MHz  
500 ± 10.0  
1000 ± 20  
6000 ±120  
-1000  
-6000  
NOTES: Any delay between 10 and 6000 ns not shown is also available.  
2006 Data Delay Devices  
Doc #06018  
5/10/2006  
DATA DELAY DEVICES, INC.  
1
3 Mt. Prospect Ave. Clifton, NJ 07013  
1234

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