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3CP0C02FREQ2NSG PDF预览

3CP0C02FREQ2NSG

更新时间: 2024-11-06 19:19:15
品牌 Logo 应用领域
艾迪悌 - IDT 机械振荡器
页数 文件大小 规格书
2页 145K
描述
CMOS Output Clock Oscillator, 100MHz Min, 133MHz Max, GREEN, SMD, 4 PIN

3CP0C02FREQ2NSG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:ActiveReach Compliance Code:compliant
风险等级:5.71其他特性:STANDBY; TUBE; SUPPLY VOLTAGE 1.8 AND 2.5 V ALSO AVAILABLE
最长下降时间:1.9 ns频率调整-机械:NO
频率稳定性:100%JESD-609代码:e3
安装特点:SURFACE MOUNT最大工作频率:133 MHz
最小工作频率:100 MHz最高工作温度:70 °C
最低工作温度:振荡器类型:CMOS
输出负载:4 pF物理尺寸:5.0mm x 3.2mm x 0.85mm
最长上升时间:1.9 ns标称供电电压:3.3 V
表面贴装:YES最大对称度:40/60 %
端子面层:Matte Tin (Sn)Base Number Matches:1

3CP0C02FREQ2NSG 数据手册

 浏览型号3CP0C02FREQ2NSG的Datasheet PDF文件第2页 
CrystalFree™ Oscillator  
3CP0C02  
Ultra Low Power Oscillators  
PRELIMINARY DATA SHEET  
Features  
. Frequency Range:  
. Output Type:  
4 to 133 MHz  
CMOS  
. Frequency Tolerance:  
. Supply Voltage:  
. Power Consumption:  
. Standby Current:  
. Standard Package:  
± 100 ppm  
1.8 to 3.3 V  
1.9 mA (1.8 V)  
< 1 uA  
5.0 x 3.2 mm  
. Operating Temperature: 0 to 70 °C  
This product is rated “Green”, please contact  
factory for environmental compliancy information  
-20 to 70 °C  
Specification  
Parameter  
Symbol  
VDD  
Specifications  
2.5 V  
4 to 133 MHz  
± 100 ppm  
2.0 mA  
Conditions  
Supply Voltage  
Output Frequency  
Frequency Stability  
Supply Current  
Quiescent Current  
Input LOW level  
Input HIGH level  
Output LOW level  
Output HIGH level  
Rise/Fall Time  
1.8 V  
3.3 V  
Nominal  
FOUT  
FSTB  
IDD  
ISTBY  
VIL  
VIH  
VOL  
VOH  
TR /TF  
See ordering code  
Total Frequency Stability*  
Typical; No load condition; 25°C  
STBY# = GND  
1.9 mA  
2.2 mA  
1 uA  
0.3 VDD (max)  
At STBY# pin  
0.7 VDD (min)  
0.1 VDD (max)  
0.9 VDD (min)  
2.3ns  
45% / 55%  
40% / 60%  
100 us  
IOL = - 1mA  
IOH = 1mA  
2.75ns  
1.9ns  
20% to 80% x VDD. Output load (CL) = 4pF  
For frequencies < 100MHz;  
For frequencies > 100MHz;  
Output valid time after VDD meets the specified range & STBY# transition  
4pF load; 75MHz  
SYM  
Symmetry  
Start-up time  
Period Jitter  
Cycle to Cycle Jitter  
TST  
PJRMS  
CCJMAX  
17 ps  
120 ps  
6 ps  
50 ps  
5 ps  
40 ps  
4pF load; 75MHz  
* Stability over temperature, supply variation, 3x reflow, load variation, aging (10 years)  
Package Outline and Dimensions  
Typical PCB Land Pattern  
Pin #1 ID  
Chamfer  
0.5 x 45°  
3.20 ±0.05  
0.90 ±0.05  
1.20 ±0.05  
0.85 ±0.05  
0.0-0.05  
2.2  
STBY#  
GND  
VDD  
OUT  
5.0 x 3.2  
(mm)  
4L SMD  
5.0 x 3.2mm  
5.00 ±0.05  
2.54  
0.203 Ref.  
1.4  
Top View  
Bottom View  
Side View  
April 1, 2011  
www.IDT.com  
©2011 Integrated Device Technology, Inc  

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