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2N5564-E3 PDF预览

2N5564-E3

更新时间: 2024-02-01 00:44:18
品牌 Logo 应用领域
威世 - VISHAY 晶体小信号场效应晶体管
页数 文件大小 规格书
6页 94K
描述
Matched N-Channel JFET Pairs

2N5564-E3 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:,Reach Compliance Code:unknown
风险等级:5.45Is Samacsys:N
FET 技术:JUNCTIONJESD-609代码:e3
湿度敏感等级:1最高工作温度:200 °C
极性/信道类型:N-CHANNEL最大功率耗散 (Abs):0.325 W
子类别:FET General Purpose Small Signal表面贴装:NO
端子面层:Matte Tin (Sn)Base Number Matches:1

2N5564-E3 数据手册

 浏览型号2N5564-E3的Datasheet PDF文件第1页浏览型号2N5564-E3的Datasheet PDF文件第3页浏览型号2N5564-E3的Datasheet PDF文件第4页浏览型号2N5564-E3的Datasheet PDF文件第5页浏览型号2N5564-E3的Datasheet PDF文件第6页 
2N5564/5565/5566  
Vishay Siliconix  
SPECIFICATIONS (T = 25_C UNLESS OTHERWISE NOTED)  
A
Limits  
2N5564  
2N5565  
2N5566  
Parameter  
Static  
Symbol  
Test Conditions  
Typa Min Max Min Max Min Max Unit  
Gate-Source  
V
I
= 1 mA, V = 0 V  
55  
2  
40  
0.5  
5
40  
0.5  
5
40  
0.5  
5
(BR)GSS  
G
DS  
Breakdown Voltage  
V
Gate-Source  
Cutoff Voltage  
V
V
= 15 V, I = 1 nA  
DS D  
3  
3  
3  
GS(off)  
Saturation Drain  
I
V
= 15 V, V = 0 V  
DS GS  
20  
mA  
30  
30  
30  
DSS  
b
Current  
V
= 20 V, V = 0 V  
5  
10  
3  
100  
200  
100  
200  
100  
200  
pA  
nA  
pA  
nA  
GS  
DS  
Gate Reverse Current  
Gate Operating Current  
I
GSS  
T
= 150_C  
A
V
= 15 V, I = 2 mA  
D
DG  
c
I
G
T
A
= 125_C  
1  
Drain-Source  
On-Resistance  
r
V
= 0 V, I = 1 mA  
50  
1.2  
0.7  
100  
1
100  
1
100  
1
W
DS(on)  
GS  
D
c
Gate-Source Voltage  
V
V
= 15 V, I = 2 mA  
DG D  
GS  
V
Gate-Source  
Forward Voltage  
V
I = 2 mA , V = 0 V  
G DS  
GS(F)  
Dynamic  
Common-Source  
g
9
7.5  
12.5  
45  
7.5  
12.5  
45  
7.5  
12.5  
45  
mS  
fs  
Forward Transconductance  
V
V
= 15 V, I = 2 mA  
D
DS  
DS  
f = 1 kHz  
Common-Source  
Output Conductance  
g
os  
35  
mS  
Common-Source  
Forward Transconductance  
= 15 V, I = 2 mA  
D
f = 100 MHz  
g
fs  
8.5  
10  
mS  
7
7
7
d
Common-Source  
Input Capacitance  
C
iss  
12  
3
12  
3
12  
3
V
V
= 15 V, I = 2 mA  
D
f = 1 MHz  
DS  
DS  
pF  
Common-Source  
Reverse Transfer  
Capacitance  
C
rss  
2.5  
12  
Equivalent Input  
Noise Voltage  
= 15 V, I = 2 mA  
D
f = 10 Hz  
nV  
Hz  
e
50  
1
50  
1
50  
1
n
Noise Figure  
NF  
R
G
= 10 MW  
dB  
Matching  
Differential  
|
|
V
–V  
V
V
= 15 V, I = 2 mA  
5
10  
25  
20  
50  
mV  
DG  
DG  
D
GS1 GS2  
Gate-Source Voltage  
Gate-Source Voltage  
Differential Change  
with Temperature  
|
|
D V  
–V  
mV/  
_C  
= 15 V, I = 2 mA  
D
= 55 to 125_C  
GS1 GS2  
10  
T
A
DT  
I
Saturation Drain  
DSS1  
V
= 15 V, V = 0 V  
GS  
0.98  
0.95  
0.95  
1
1
0.95  
0.90  
1
1
0.95  
0.90  
1
1
DS  
c
Current Ratio  
I
DSS2  
g
g
V
= 15 V, I = 2 mA  
D
f = 1 kHz  
fs1  
DS  
V
Transconductance Ratio  
Common Mode  
0.98  
76  
fs2  
= 10 to 20 V  
D
DG  
I
CMRR  
dB  
c
Rejection Ratio  
= 2 mA  
Notes  
a. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.  
b. Pulse test: PW v300 ms duty cycle v3%.  
NCBD  
c. This parameter not registered with JEDEC.  
d. Not a production test.  
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation  
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum  
rating conditions for extended periods may affect device reliability.  
Document Number: 70254  
S-50150—Rev. E, 24-Jan-05  
www.vishay.com  
2
 

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