2N5565

更新时间： 2024-01-07 08:47:03

品牌	Logo	应用领域
威世 - VISHAY		晶体晶体管放大器
页数	文件大小	规格书
5页	49K
描述
Matched N-Channel JFET Pairs

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2N5565 数据手册

2N5564/5565/5566

Vishay Siliconix

Matched N-Channel JFET Pairs

PRODUCT SUMMARY

Part Number V_GS(off)(V) V_(BR)GSSMin (V) g_fsMin (mS) I_GTyp (pA) jV_GS1– V_GS2j Max (mV)

2N5564

2N5565

2N5566

–0.5 to –3

–40

7.5

–3

FEATURES

BENEFITS

APPLICATIONS

D Two-Chip Design

D Tight Differential Match vs. Current

D Wideband Differential Amps

D High Slew Rate

D Improved Op Amp Speed, Settling Time

D High-Speed,

Accuracy

Temp-Compensated,

Single-Ended Input Amps

D High-Speed Comparators

D Impedance Converters

D Matched Switches

D Low Offset/Drift Voltage

D Low Gate Leakage: 3 pA

D Low Noise: 12 nV⁄√Hz @ 10 Hz

D Good CMRR: 76 dB

D Minimum Parasitics

D Minimum Input Error/Trimming Requirement

D Insignificant Signal Loss/Error Voltage

D High System Sensitivity

D Minimum Error with Large Input Signals

D Maximum High Frequency Performance

DESCRIPTION

The 2N5564/5565/5566 are matched pairs of JFETs mounted

in a TO-71 package. This two-chip design reduces parasitics

for good performance at high frequency while ensuring

The hermetically-sealed TO-71 package is available with full

military processing (see Military Information).

extremely tight matching.

This series features high

breakdown voltage (V_(BR)DSStypically > 55 V), high gain

(typically > 9 mS), and <5 mV offset between the two die.

For similar products see the low-noise U/SST401 series, and

the low-leakage 2N5196/5197/5198/5199 data sheets.

TO-71

Top View

ABSOLUTE MAXIMUM RATINGS

Gate-Drain, Gate-Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40 V

Gate-Gate Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "80 V

Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . –55 to 150_C

Power Dissipation :

Per Side . . . . . . . . . . . . . . . . . . . . . . . . 325 mW

Total . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 mW

Notes

Lead Temperature ( / ” from case for 10 sec.) . . . . . . . . . . . . . . . . . . 300 _C

a. Derate 2.6 mW/_C above 25_C

b. Derate 5.2 mW/_C above 25_C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65 to 200_C

Document Number: 70254

S-04031—Rev. D, 04-Jun-01

www.vishay.com

8-1

12 3 4 5

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