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2N3957 PDF预览

2N3957

更新时间: 2024-11-24 22:49:23
品牌 Logo 应用领域
INTERFET 晶体小信号场效应晶体管放大器
页数 文件大小 规格书
1页 68K
描述
N-Channel Dual Silicon Junction Field-Effect Transistor

2N3957 技术参数

生命周期:Contact Manufacturer包装说明:CYLINDRICAL, O-MBCY-W6
Reach Compliance Code:unknown风险等级:5.38
Is Samacsys:N配置:SEPARATE, 2 ELEMENTS
FET 技术:JUNCTION最大反馈电容 (Crss):1.2 pF
JEDEC-95代码:TO-71JESD-30 代码:O-MBCY-W6
元件数量:2端子数量:6
工作模式:DEPLETION MODE最高工作温度:150 °C
封装主体材料:METAL封装形状:ROUND
封装形式:CYLINDRICAL极性/信道类型:N-CHANNEL
功耗环境最大值:0.5 W最大功率耗散 (Abs):0.5 W
认证状态:Not Qualified子类别:FET General Purpose Small Signal
表面贴装:NO端子形式:WIRE
端子位置:BOTTOM晶体管应用:AMPLIFIER
晶体管元件材料:SILICONBase Number Matches:1

2N3957 数据手册

  
B-6  
01/99  
2N3957, 2N3958  
N-Channel Dual Silicon Junction Field-Effect Transistor  
Absolute maximum ratings at T = 25¡C  
¥ Low and Medium Frequency  
Differential Amplifiers  
¥ High Input Impedance  
Amplifiers  
A
Reverse Gate Source & Reverse Gate Drain Voltage  
– 50 V  
50 mA  
250 mW  
500 mW  
4.3 mW/°C  
Gate Current  
Total Device Power Dissipation (each side)  
@ 85°C Case Temperature (both sides)  
Power Derating (both sides)  
At 25°C free air temperature:  
Static Electrical Characteristics  
2N3957  
2N3958  
Process NJ16  
Test Conditions  
I = – 1 µA, V = ØV  
Min Max Min Max Unit  
Gate Source Breakdown Voltage  
V
– 50  
– 50  
V
– 100 pA  
– 500 nA  
– 50 pA  
– 250 nA  
(BR)GSS  
G
DS  
– 100  
– 500  
– 50  
V
= – 30V, V = ØV  
GS  
DS  
Gate Reverse Current  
I
GSS  
V
= – 30V, V = ØV  
T = 125°C  
A
GS  
DS  
V
= 20V, I = 200 µA  
DS  
D
Gate Operating Current  
Gate Source Voltage  
I
G
– 250  
– 4.2  
V
= 20V, I = 200 µA  
T = 125°C  
DS  
D
A
– 4.2  
V
V
V
= 20V, I = 50 µA  
DS  
D
V
GS  
– 0.5 – 4 – 0.5 – 4  
– 1 – 4.5 – 1 – 4.5  
V
= 20V, I = 200 µA  
DS  
D
Gate Source Cutoff Voltage  
V
V
V
= 20V, I = 1 nA  
GS(OFF)  
DS  
D
Gate Source Forward Voltage  
Drain Saturation Current (Pulsed)  
V
2
5
2
5
V
V
= Ø, I = 1 mA  
GS(F)  
DS  
G
I
0.5  
0.5  
mA  
V
= 20V, V = ØV  
DSS  
DS  
GS  
Dynamic Electrical Characteristics  
1000 3000 1000 3000 µS  
V
= 20V, V = ØV  
f = 1 kHz  
Common Source  
Forward Transconductance  
DS  
GS  
g
g
fs  
1000  
1000  
µS  
µS  
pF  
pF  
V
= 20V, V = ØV  
f = 200 MHz  
f = 1 kHz  
DS  
GS  
Common Source Output Conductance  
Common Source Input Capacitance  
Drain Gate Capacitance  
35  
4
35  
4
V
= 20V, V = ØV  
os  
DS  
GS  
C
V
= 20V, V = ØV  
f = 1 MHz  
f = 1 MHz  
iss  
DS  
GS  
C
1.5  
1.5  
V
= 10V, I = ØA  
dgo  
DS  
S
Common Source  
C
1.2  
0.5  
1.2  
0.5  
pF  
V
= 20V, V = ØV  
f = 1 MHz  
f = 100 Hz  
rss  
DS  
GS  
Reverse Transfer Capacitance  
V
= 20V, V = ØV  
DS  
GS  
Noise Figure  
NF  
dB  
nA  
R = 10MΩ  
G
Differential Gate Current  
| I – I  
|
10  
1
10  
1
V
= 20V, I = 200 µA  
T = 125°C  
G1  
G2  
DS  
D
A
Saturation Drain Current Ratio  
Differential Gate Source Voltage  
I
/ I  
0.9  
0.9  
0.85  
0.85  
V
= 20V, V = ØV  
DSS1 DSS2  
| V – V  
DS  
GS  
|
GS2  
20  
25  
mV  
mV  
V
= 20V, I = 200 µA  
GS1  
DS  
D
T = 25°C  
A
6
8
V
= 20V, I = 200 µA  
DS  
D
to – 55°C  
V – V  
Differential Gate Source  
Voltage with Temperature  
GS1 GS2  
T  
T = 25°C  
A
7.5  
1
10  
1
mV  
V
= 20V, I = 200 µA  
DS  
D
to 125°C  
Transconductance Ratio  
g
/ g  
V
= 20V, I = 200 µA  
f = 1 kHz  
fs1 fs2  
DS  
D
TOÐ71 Package  
See Section G for Outline Dimensions  
Pin Configuration  
1 Source, 2 Drain, 3 Gate, 5 Source,  
6 Drain, 7 Gate  
1000 N. Shiloh Road, Garland, TX 75042  
(972) 487-1287 FAX (972) 276-3375  
www.interfet.com  

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