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24LCS52-ST PDF预览

24LCS52-ST

更新时间: 2024-11-21 12:52:43
品牌 Logo 应用领域
美国微芯 - MICROCHIP /
页数 文件大小 规格书
36页 822K
描述
Single Supply with Operation Down to 1.8V

24LCS52-ST 数据手册

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24AA52/24LCS52  
2K 2.2V I2CSerial EEPROM with Software Write-Protect  
Device Selection Table  
Description:  
The Microchip Technology Inc. 24AA52/24LCS52  
(24XXX52*) is a 2 Kbit Electrically Erasable PROM  
capable of operation across a broad voltage range  
(1.8V to 5.5V). This device has a software write-protect  
feature for the lower half of the array, as well as an  
external pin that can be used to write-protect the entire  
array. The software write-protect feature is enabled by  
sending the device a special command. Once this  
feature has been enabled, it cannot be reversed. In  
addition to the software protect feature, there is a WP  
pin that can be used to write-protect the entire array,  
regardless of whether the software write-protect  
register has been written or not. This allows the system  
designer to protect none, half, or all of the array,  
depending on the application. The device is organized  
as one block of 256 x 8-bit memory with a 2-wire serial  
interface. Low-voltage design permits operation down  
to 1.8V, with standby and active currents of only 1 A  
and 1 mA, respectively. The 24XXX52 also has a page  
write capability for up to 16 bytes of data. The 24XXX52  
is available in the standard 8-pin PDIP, surface mount  
SOIC, TSSOP, MSOP, DFN and TDFN packages.  
Part  
Number  
VCC  
Range  
Max Clock  
Frequency  
Temp  
Ranges  
24AA52  
1.8-5.5  
2.2-5.5  
400 kHz(1)  
400 kHz  
I
I
24LCS52  
Note 1: 100 kHz for VCC <2.2V  
Features:  
• Single Supply with Operation Down to 1.8V  
• Low-Power CMOS Technology:  
- 1 mA active current, typical  
- 1 A standby current, typical (I-temp)  
• Organized as 1 Block of 256 Bytes (256 x 8)  
• Software Write Protection for Lower 128 Bytes  
• Hardware Write Protection for Entire Array  
• 2-Wire Serial Interface Bus, I2C™ Compatible  
• Schmitt Trigger Inputs for Noise Suppression  
• Output Slope Control to Eliminate Ground Bounce  
• 100 kHz (24AA52) and 400 kHz (24LCS52)  
Compatibility  
Block Diagram  
• Self-Timed Write Cycle (including auto-erase)  
• Page Write Buffer for up to 16 Bytes  
• ESD Protection > 4,000V  
WP  
A0 A1 A2  
HV Generator  
• 1,000,000 Erase/Write Cycles  
• Data Retention > 200 Years  
Software write  
protected area  
(00h-7Fh)  
I/O  
Control  
Logic  
Memory  
Control  
Logic  
• 8-Lead PDIP, SOIC, TSSOP, MSOP, DFN and  
TDFN Packages  
XDEC  
Standard  
Array  
• Pb-Free Finishes Available  
SDA SCL  
• Available for Extended Temperature Ranges:  
- Industrial (I): -40°C to +85°C  
VCC  
VSS  
Write-Protect  
Circuitry  
YDEC  
Package Types  
PDIP/SOIC/TSSOP/MSOP/DFN/TDFN  
Sense Amp.  
R/W Control  
A0  
A1  
1
2
3
4
8
7
6
5
VCC  
WP  
1
VCC  
WP  
A0  
A1  
8
7
6
5
2
3
4
SCL  
SDA  
A2  
A2  
SCL  
SDA  
VSS  
VSS  
*24XXX52 is used in this document as a generic part number  
for the 24AA52/24LCS52 devices.  
1996-2011 Microchip Technology Inc.  
DS21166K-page 1  

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