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24LC256TISM

更新时间: 2024-11-06 12:31:43
品牌 Logo 应用领域
美国微芯 - MICROCHIP 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
42页 1254K
描述
256K I2C™ CMOS Serial EEPROM

24LC256TISM 数据手册

 浏览型号24LC256TISM的Datasheet PDF文件第2页浏览型号24LC256TISM的Datasheet PDF文件第3页浏览型号24LC256TISM的Datasheet PDF文件第4页浏览型号24LC256TISM的Datasheet PDF文件第5页浏览型号24LC256TISM的Datasheet PDF文件第6页浏览型号24LC256TISM的Datasheet PDF文件第7页 
24AA256/24LC256/24FC256  
256K I2C™ CMOS Serial EEPROM  
Temperature Ranges:  
Device Selection Table  
- Industrial (I):  
- Automotive (E):  
-40C to +85C  
-40C to +125C  
Part  
VCC  
Max. Clock  
Frequency  
Temp.  
Ranges  
Number  
Range  
Description:  
24AA256  
24LC256  
24FC256  
1.7-5.5V  
2.5-5.5V  
1.7-5.5V  
400 kHz(1)  
400 kHz  
1 MHz(2)  
I, E  
I, E  
I
The Microchip Technology Inc. 24AA256/24LC256/  
24FC256 (24XX256*) is a 32K x 8 (256 Kbit) Serial  
Electrically Erasable PROM, capable of operation  
across a broad voltage range (1.7V to 5.5V). It has  
been developed for advanced, low-power applications  
such as personal communications or data acquisition.  
This device also has a page write capability of up to 64  
bytes of data. This device is capable of both random  
and sequential reads up to the 256K boundary.  
Functional address lines allow up to eight devices on  
the same bus, for up to 2 Mbit address space. This  
device is available in the standard 8-pin plastic DIP,  
SOIC, TSSOP, MSOP, DFN and TDFN packages. The  
24AA256 is also available in the 8-lead Chip Scale  
package.  
Note 1: 100 kHz for VCC < 2.5V.  
2: 400 kHz for VCC < 2.5V.  
Features:  
• Single Supply with Operation Down to 1.7V for  
24AA256 and 24FC256 Devices, 2.5V for  
24LC256 Devices  
• Low-Power CMOS Technology:  
- Active current 400 uA, typical  
- Standby current 100 nA, typical  
• 2-Wire Serial Interface, I2CCompatible  
• Cascadable up to Eight Devices  
• Schmitt Trigger Inputs for Noise Suppression  
• Output Slope Control to Eliminate Ground Bounce  
• 100 kHz and 400 kHz Clock Compatibility  
• Page Write Time 5 ms Max.  
Block Diagram  
A0 A1A2WP  
HV Generator  
I/O  
Control  
Logic  
• Self-Timed Erase/Write Cycle  
Memory  
Control  
Logic  
EEPROM  
Array  
XDEC  
• 64-Byte Page Write Buffer  
• Hardware Write-Protect  
Page Latches  
• ESD Protection >4000V  
I/O  
• More than One Million Erase/Write Cycles  
• Data Retention >200 years  
SCL  
YDEC  
SDA  
• Factory Programming Available  
• Packages Include 8-lead PDIP, SOIC, DFN,  
TDFN, TSSOP and MSOP  
VCC  
Sense Amp.  
R/W Control  
VSS  
• Pb-Free and RoHS Compliant  
Package Types  
TSSOP/MSOP(1)  
DFN/TDFN  
CS (Chip Scale)(2)  
VCC A1 A0  
PDIP/SOIC  
A0  
1
8
VCC  
1
2
3
4
A0  
A1  
8
7
6
5
VCC  
WP  
1
2
8
7
A0  
A1  
VCC  
WP  
1
2
3
A1  
A2  
2
3
4
7
6
5
WP  
4
5
WP  
A2  
A2  
SCL  
SDA  
8
6
7
SCL  
SDA  
3
4
6
5
A2  
SCL  
SDA  
SDA SCL VSS  
VSS  
VSS  
VSS  
(TOP DOWN VIEW,  
BALLS NOT VISIBLE)  
Note 1: * Pins A0 and A1 are no connects for the MSOP package only.  
Note 2: Available in I-temp, “AA” only.  
*24XX256 is used in this document as a generic part number for the 24AA256/24LC256/24FC256 devices.  
1998-2013 Microchip Technology Inc.  
DS20001203T-page 1  

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