Datasheet > 24LC08BT-I/SNA35

24LC08BT-I/SNA35

更新时间： 2024-02-20 00:22:59

品牌	Logo	应用领域
美国微芯 - MICROCHIP		可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
页数	文件大小	规格书
40页	1104K
描述
1K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 3.90 MM, ROHS COMPLIANT, PLASTIC, SOIC-8

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24LC08BT-I/SNA35 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	SOP,	针数：	8
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.51	风险等级：	5.21
其他特性：	100K ERASE/WRITE CYCLES MIN; CAN BE ORGANIZED AS 4 BLOCKS OF 256 BYTES; DATA RETENTION > 40 YEARS	最大时钟频率 (fCLK)：	0.4 MHz
数据保留时间-最小值：	40	JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e3	长度：	4.9 mm
内存密度：	8192 bit	内存集成电路类型：	EEPROM
内存宽度：	8	湿度敏感等级：	1
功能数量：	1	端子数量：	8
字数：	1024 words	字数代码：	1000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	1KX8
输出特性：	OPEN-DRAIN	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	并行/串行：	SERIAL
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	1.75 mm	串行总线类型：	I2C
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	2.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	40	宽度：	3.9 mm
最长写入周期时间 (tWC)：	5 ms	Base Number Matches：	1

24LC08BT-I/SNA35 数据手册

浏览型号24LC08BT-I/SNA35的Datasheet PDF文件第10页

浏览型号24LC08BT-I/SNA35的Datasheet PDF文件第11页

24AA08/24LC08B

words prior to generating the Stop condition, the

address counter will roll over and the previously

received data will be overwritten. As with the byte write

operation, once the Stop condition is received an

internal write cycle will begin (Figure 6-2).

6.0

6.1

WRITE OPERATION

Byte Write

Following the Start condition from the master, the

device code (4 bits), the block address (3 bits) and the

R/W bit, which is a logic-low, is placed onto the bus by

the master transmitter. This indicates to the addressed

slave receiver that a byte with a word address will

follow once it has generated an Acknowledge bit during

the ninth clock cycle. Therefore, the next byte transmit-

ted by the master is the word address and will be

written into the Address Pointer of the 24XX08. After

receiving another Acknowledge signal from the

24XX08, the master device will transmit the data word

to be written into the addressed memory location. The

24XX08 acknowledges again and the master

generates a Stop condition. This initiates the internal

write cycle and, during this time, the 24XX08 will not

generate Acknowledge signals (Figure 6-1).

Note:

Page write operations are limited to writ-

ing bytes within a single physical page,

regardless of the number of bytes

actually being written. Physical page

boundaries start at addresses that are

integer multiples of the page buffer size

(or ‘page-size’) and end at addresses that

are integer multiples of [page size – 1]. If

a Page Write command attempts to write

across a physical page boundary, the

result is that the data wraps around to the

beginning of the current page (overwriting

data previously stored there), instead of

being written to the next page, as might be

expected. It is therefore necessary for the

application software to prevent page write

operations that would attempt to cross a

page boundary.

6.2

Page Write

The write control byte, word address and the first data

byte are transmitted to the 24XX08 in the same way as

in a byte write. However, instead of generating a Stop

condition, the master transmits up to 16 data bytes to

the 24XX08, which are temporarily stored in the on-

chip page buffer and will be written into memory once

the master has transmitted a Stop condition. Upon

receipt of each word, the four lower-order Address

Pointer bits are internally incremented by ‘1’. The

higher-order 7 bits of the word address remain

constant. If the master should transmit more than 16

6.3

Write Protection

The WP pin allows the user to write-protect the entire

array (000-3FF) when the pin is tied to VCC. If the pin is

tied to VSS the write protection is disabled.

The Chip Select package does not support the write-

protect feature.

FIGURE 6-1: BYTE WRITE

Bus Activity

Master

Control

Byte

Word

Address

Data

1 0 1

X B1B0 0

SDA Line

Bus Activity

Block

Select

Bits

x= “don’t care”

FIGURE 6-2: PAGE WRITE

Bus Activity

Master

Control

Byte

Word

Address (n)

Data (n)

Data (n + 1)

Data (n + 15)

SDA Line

10 XB1

Bus Activity

Block

Select

Bits

x= “don’t care”

DS21710K-page 8

 2002-2012 Microchip Technology Inc.

1...5 6 789 10 11...40

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与24LC08BT-I/SNA35相关器件

型号	品牌	描述	获取价格	数据表
24LC08BT-I/SNG	MICROCHIP	8K IC SERIAL EEPROM	获取价格
24LC08BT-I/SNROC	MICROCHIP	1K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 3.90 MM, ROHS COMPLIANT, PLASTIC, SOIC-8	获取价格
24LC08BT-I/SNRVE	MICROCHIP	8K 2-Wire SERIAL EEPROM, -40C to +85C, 8-SOIC 150mil, T/R	获取价格
24LC08BTI/ST	MICROCHIP	256 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 4.40 MM, ROHS COMPLIANT, PLASTIC, TSSOP-8	获取价格
24LC08BT-I/ST	MICROCHIP	8K IC SERIAL EEPROM	获取价格
24LC08BT-I/STG	MICROCHIP	8K IC SERIAL EEPROM	获取价格

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