Enhanced PCI Bus Multimedia Controller (Low-Voltage)
4.3.3 PostOffice Handshaking Protocol
4.2 Video DMA Controller
4.2.1 Pixel Bursts
The ZR36067-LV PostOffice handshaking protocol, implement-
ed over the GuestBus, allows host accesses to relatively slow
The packed pixels are transferred directly to the display memory
(or to the system memory), using PCI DMA bursts. Both Little
and “Gib” Endian formats are supported where applicable (Refer
to the PCI Multimedia Design Guide, Revision 1.0).
guest devices, with no degradation of the PCI bus performance.
4.3.4 Still Transfer Mechanism
The ZR36067-LV supports a dedicated Still Transfer port, by
means of which the host writes (reads) image pixels in JPEG Still
Image Compression (Decompression) mode. The Still Transfer
port is mapped inside the ASR area, and a special controller
interconnects this port to the ZR36067-LV’s extended video bus
(24 bits RGB). The Still Transfer handshake protocol enables
high rate pixels transfer between the system memory and the
JPEG processor via the ZR36067-LV.
4.2.2 Display Modes
The display mode can be configured to either emulated inter-
laced video (both input fields are displayed simultaneously on
the non-interlaced monitor) or single field display. The latter is
appropriate for motion artifact elimination when displaying live or
decompressed Motion JPEG video.
4.3.5 I2C Port
4.2.3 Frame Grabbing
A software-driven I2C port allows controlling of I2C devices.
The ZR36067-LV can grab video frames (scaled or non scaled),
or fields, in any of the pixel formats listed above, directly into
system memory, eliminating the need for memory on the add-in
board.
4.3.6 Interrupt Manager
Interrupt requests associated with several internal and external
conditions are sent to the host via the PCI bus (using INTA).
Selection of interrupt originators is programmable.
4.2.4 Overlay Control
Graphics overlay is supported, in that display memory areas that
are “owned” by graphics applications, may not be loaded with
video pixels, allowing true windowing and overlay. The software
driver prepares a masking map of the video rectangle, and the
ZR36067-LV uses this map for masking decision, when transfer-
ring the pixels to the display memory.
4.4 Code DMA Controller
The ZR36067-LV includes a DMA channel for transferring data
between the system memory and a selected device on the Code
Bus or GuestBus. Two configurations are supported:
• MPEG mode. The data flow is unidirectional, from the sys-
tem memory, to the ZR36067-LV’s GuestBus.
4.3 Host Control/Communication Services
4.3.1 Application-Specific Registers (ASRs)
• JPEG mode. The data flow is bidirectional, and the direction
is determined by the selected sub-mode. In JPEG Compres-
sion, the data flows from the Codec bus to the system
memory. In JPEG Decompression, the data flows from the
system memory to the Codec bus.
The name “application-specific” distinguishes these registers
from the PCI configuration space registers. These memory
mapped registers provide the host software with full control over
the operation of the ZR36067-LV. The ZR36067-LV claims a
contiguous space of 4 KBytes in system memory.
4.4.1 MPEG Mode
In MPEG mode, the data flows from the system memory to the
ZR36067-LV’s GuestBus. Typically, this would be a compressed
bitstream, to be decompressed by a device such as an MPEG
decoder attached to the GuestBus. Other examples are sampled
audio (WAV data), MIDI token stream, etc. Temporary latencies
on the PCI bus or the GuestBus are handled without loss of data.
4.3.2 GuestBus
Host software control over non-PCI devices, such as a Motion
JPEG codec, an MPEG decoder, a video encoder, etc., is done
through the ZR36067-LV’s GuestBus. Host accesses to these
“guest” devices, mapped as application specific registers inside
the ZR36067-LV, are output as GuestBus cycles. Such
accesses can either use the PostOffice handshaking protocol, or
the Code DMA Controller. The first method is adequate for com-
mands, configuration data, etc., while the second method
provides a faster channel, and is intended for continuous
transfer of data such as a compressed bitstream.
The GuestBus master simultaneously serves the PostOffice
accesses and the code DMA transfers: DMA transfers are
viewed as the “main” task of the GuestBus master, while any
number of PostOffice requests may occasionally interrupt the
DMA traffic.
The DMA controller supports both auto-initialized (cyclic) block
transfers, or single block transfers. The size of the destination
block in main memory can be selected out of several possible
sizes, ranging from 8 KBytes up to 256 KBytes. The destination
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