Datasheet > ZR36067PQC-LV

ZR36067PQC-LV

更新时间： 2024-01-05 12:11:42

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
50页	364K
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Peripheral IC

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ZR36067PQC-LV 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	FQFP,	针数：	208
Reach Compliance Code：	unknown	风险等级：	5.82
地址总线宽度：	32	总线兼容性：	PCI; I2C
外部数据总线宽度：	32	JESD-30 代码：	S-PQFP-G208
长度：	28 mm	端子数量：	208
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	FQFP
封装形状：	SQUARE	封装形式：	FLATPACK, FINE PITCH
认证状态：	Not Qualified	座面最大高度：	4.15 mm
最大供电电压：	5.25 V	最小供电电压：	4.75 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	宽度：	28 mm
uPs/uCs/外围集成电路类型：	BUS CONTROLLER, PCI	Base Number Matches：	1

ZR36067PQC-LV 数据手册

Enhanced PCI Bus Multimedia Controller (Low-Voltage)

2.0 ARCHITECTURAL OVERVIEW

The ZR36067-LV architecture contains two main data paths, the

video path and the code path. The incoming video is processed

along the video path and transferred to the graphics display

memory using PCI DMA bursts.

In JPEG Decompression modes the code stream flows in the

opposite direction, from the system memory to the ZR36067-LV

Code FIFO. The Codec Front End reads out the Code FIFO byte

by byte onto the Code Bus.

The ZR36067-LV Video Front End samples the video bus within

a programmable active field window, defined with respect to the

video synchronization signals. An optional vertical and horizon-

tal smooth scale down can be applied, in order to support

variable image sizes and variable PCI video data rate. The

scaled video stream can be converted to various RGB formats.

The converted pixels are packed and stored in a 256-byte Video

FIFO, organized as 64 32-bit doublewords. The stored video

pixels are read from the Video FIFO and transferred to the

graphics display memory according to a display masking map

controlled by and stored inside the ZR36067-LV.

In MPEG Playback mode, the code stream is transferred to the

ZR36067-LV Code FIFO from the system memory. The code

bytes are read from the Code FIFO out to the Guest Bus.

The ZR36067-LV video and the code paths operate simulta-

neously while the ZR36067-LV arbitrates the PCI bus requests

for each process.

Besides managing the Video and Code paths, the ZR36067-LV

bridges the host CPU to peripheral devices (known as Guests).

Using a dedicated handshaking mechanism (the “PostOffice”

mechanism), host accesses to an internal ZR36067-LV register

are reflected to the Guest Bus in order to enable indirect host

read and write operations to the Guests.

The Code path is bidirectional. The data flow direction depends

on the mode of operation. The code stream (MPEG or JPEG) is

transferred between system memory and the internal Code

FIFO of the ZR36067-LV using PCI DMA bursts. The ZR36067-

LV controls the transfer and addressing in both directions. The

Code FIFO size is 640 bytes, organized as 160 doublewords.

The ZR36067-LV contains a dedicated “Still Transfer” port which

enables data flow between the PCI interface and the Video Front

End. Using a specific handshake protocol, the host software

may transfer digitized video (RGB pixels) from the system

memory to the Video bus, and vice versa. This path enables very

fast transfer of still video images to be compressed or decom-

pressed by the JPEG codec.

In JPEG Compression modes the ZR36067-LV Codec Front

End fills the Code FIFO. From the Code FIFO the code is trans-

ferred to the system memory, field by field.

Video DMA

Controller

VCLK, VCLKx2

VSYNC, HSYNC

Video Front End

Video Input

Processor

RTBSY

Video FIFO

(VFE)

START, PXEN

Y[7:0]

UV[7:0]

B[7:0]

Application

Specific

GPIO[7:0]

Registers

SCL

I C Port

SDA

GCS[7:0]

GAD[2:0]

GRD, GWR

Guest Bus

GRDY

Master

Code DMA

Controller

GWS

GDAT[7:0]

Code FIFO

CEND

CCS

Codec Front End

(CFE)

CBUSY

CODE[7:0]

Interrupt

Manager

GIRQ[1:0]

Figure 2. ZR36067-LV Block Diagram

1...3 4 567 8 9...50

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