Datasheet > Z9305BX

Z9305BX

更新时间： 2024-11-06 19:47:55

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		驱动光电二极管逻辑集成电路
页数	文件大小	规格书
9页	92K
描述
PLL Based Clock Driver, PDSO8, 0.150 INCH, SOIC-8

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Z9305BX 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	SOIC	包装说明：	SOP,
针数：	8	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.84
JESD-30 代码：	R-PDSO-G8	JESD-609代码：	e4
长度：	4.93 mm	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
湿度敏感等级：	3	端子数量：	8
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	1.73 mm	表面贴装：	YES
端子面层：	NICKEL PALLADIUM GOLD	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	20	宽度：	3.94 mm
Base Number Matches：	1

Z9305BX 数据手册

Z9305/Z9309

Zero Delay Clock Buffer

Preliminary

Product Features

Product Description

•

Zero input-output propagation delay

Output-output skew less than 250 ps

Device-device skew less than 700 ps

One input drives nine outputs, grouped as 4/4/1

(Z9309)

10 MHz to 150 MHz operating range, compatible

with CPU and PCI bus frequencies

Less than 200 ps cycle-cycle jitter, compatible with

Pentium and Pentium Pro –based systems

Test Mode to bypass PLL (Z9309)

The Z9309 is a low cost 3.3V zero delay buffer

designed to distribute high speed clocks in PC system

devices and SDRAM modules and is available in a 16-

pin SOIC or TSSOP package. The Z9305 is an 8-pin

version of the Z9309 and it accepts one reference input

and drives out five low skew clocks. The devices have

an on-chip PLL which locks to an input clock on the

REF pin. The PLL feedback is on-chip and is obtained

from the CLKOUT pad.

•

The Z9309 has two banks of four outputs each, which

can be controlled by the Select inputs as shown in the

Table 1. If all output clocks are not required, Bank B can

be tri-stated. The select inputs also allow the input clock

to be directly applied to the output for chip and system

testing purposes.

Available in space-saving 16 pin 150-mil SOIC and

TSSOP package (Z9309), and 8 pin 150 Mil SOIC

package (Z9305)

Block Diagram (Z9305)

The Z9305 and Z9309 PLLs enter a Power Down mode

when there are no rising edges on the REF input. In this

state, the outputs are tri-stated and the PLL is turned

off, resulting in less than 50 uA of current draw. The

Z9309 PLL shuts down in one additional case as shown

in Table 1.

REF

PLL

CLKOUT

CLK1

CLK2

CLK3

Multiple Z9305 and Z9309 devices can accept the same

input clock and distribute it. In this case, the skew

between the outputs of two devices is guaranteed to be

less than 700 ps.

CLK4

Block Diagram (Z9309)

All outputs have less than 200 ps of cycle-cycle jitter.

The input to output propagation delay is guaranteed to

be less than 350 ps, and the output to output skew is

guaranteed to be less than 250 ps.

PLL

REF

CLKOUT

CLKA1

CONNECTION DIAGRAM

CLKA2

CLKA3

CLKA4

Select Input

Decoding

REF

CLKA1

CLKA2

VDD

CLKOUT

CLKA4

CLKA3

VDD

REF

CLK2

CLK1

GND

CLKOUT

CLK4

CLKB1

CLKB2

CLKB3

CLKB4

VDD

G N D

CLK3

CLKB1

CLKB2

CLKB4

CLKB3

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.

MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571

Rev.1.0

11/4/1999

Page 1 of 9

12 3 4 5 6 7...9

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与Z9305BX相关器件

型号	品牌	获取价格	描述	数据表
Z9305DZ	CYPRESS	获取价格	PLL Based Clock Driver, 4 True Output(s), 0 Inverted Output(s), PDSO8, 0.150 INCH, SOIC-8
Z9308-1CT	CYPRESS	获取价格	PLL Based Clock Driver, PDSO16, TSSOP-16
Z9308-1CZ	CYPRESS	获取价格	PLL Based Clock Driver, PDSO16, 0.150 INCH, SOIC-16
Z9308-2CT	CYPRESS	获取价格	PLL Based Clock Driver, PDSO16, TSSOP-16
Z9308-2CZ	CYPRESS	获取价格	PLL Based Clock Driver, PDSO16, SOIC-16
Z9308-3CT	CYPRESS	获取价格	PLL Based Clock Driver, PDSO16, TSSOP-16
Z9308-3CZ	CYPRESS	获取价格	PLL Based Clock Driver, PDSO16, SOIC-16
Z9308-4CT	CYPRESS	获取价格	PLL Based Clock Driver, PDSO16, TSSOP-16
Z9309CT	CYPRESS	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PDSO16, TSSOP-16
Z9309CZ	CYPRESS	获取价格	Clock Driver,

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