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Z86E0612PSC PDF预览

Z86E0612PSC

更新时间: 2024-11-08 22:24:03
品牌 Logo 应用领域
ZILOG 微控制器
页数 文件大小 规格书
9页 66K
描述
CMOS Z8 OTP MICROCONTROLLERS

Z86E0612PSC 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP18,.3针数:18
Reach Compliance Code:unknownHTS代码:8542.31.00.01
风险等级:5.46具有ADC:NO
其他特性:OPTIONAL LOW EMI MODE; EPROM PROTECT; TWO STANDBY MODES地址总线宽度:
位大小:8边界扫描:NO
CPU系列:Z8最大时钟频率:12 MHz
DAC 通道:NODMA 通道:NO
外部数据总线宽度:格式:FIXED POINT
集成缓存:NOJESD-30 代码:R-PDIP-T18
JESD-609代码:e0长度:22.86 mm
低功率模式:YESDMA 通道数量:
外部中断装置数量:6I/O 线路数量:14
串行 I/O 数:1端子数量:18
计时器数量:2片上数据RAM宽度:8
片上程序ROM宽度:8最高工作温度:105 °C
最低工作温度:-40 °CPWM 通道:NO
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP18,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
RAM(字节):125RAM(字数):124
ROM(单词):1024ROM可编程性:OTPROM
座面最大高度:4.24 mm速度:12 MHz
子类别:Microcontrollers最大压摆率:15 mA
最大供电电压:5.5 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
uPs/uCs/外围集成电路类型:MICROCONTROLLERBase Number Matches:1

Z86E0612PSC 数据手册

 浏览型号Z86E0612PSC的Datasheet PDF文件第2页浏览型号Z86E0612PSC的Datasheet PDF文件第3页浏览型号Z86E0612PSC的Datasheet PDF文件第4页浏览型号Z86E0612PSC的Datasheet PDF文件第5页浏览型号Z86E0612PSC的Datasheet PDF文件第6页浏览型号Z86E0612PSC的Datasheet PDF文件第7页 
PRELIMINARY  
CUSTOMER PROCUREMENT SPECIFICATION  
Z86E03/E06  
CMOS Z8® OTP  
MICROCONTROLLERS  
FEATURES  
Low-Power Consumption  
Expanded Register File (ERF)  
14 Input/Output Lines  
ROM  
(Kbytes) (Kbytes)  
RAM*  
Speed  
(MHz)  
Part  
SPI  
Z86E03  
Z86E06  
512  
1
61  
125  
No  
Yes  
8
12  
*General-Purpose  
Serial Peripheral Interface (SPI) (Z86E06 Only)  
Software Watch-Dog Timer (WDT)  
Power-On Reset (POR)  
18-Pin DIP, WIN, and SOIC Packages  
4.5- to 5.5-Volt Operating Range  
0°C to +70°C Temperature Range  
GENERAL DESCRIPTION  
The Z86E03/E06 are One-Time Programmable (OTP)  
members of the Z8® microcontroller family allowing easy  
software development, debug, and prototyping for small  
production runs that are not economically desirable with a  
masked ROM version.  
For applications demanding powerful I/O capabilities, the  
Z86E03/E06's dedicated inputand outputlines are grouped  
into two ports, and are configurable under software control  
to provide timing, status signals, or parallel I/O.  
Notes:  
All Signals with a preceding front slash, "/", are active Low, e.g.:  
B//W (WORD is active Low); /B/W (BYTE is active Low, only).  
Three address spaces, the Program Memory, Register  
File, and Expanded Register File (ERF), support a wide  
range of memory configurations. Through the ERF, the  
designer has access to four additional control registers  
that provide extra peripheral devices, I/O ports, register  
addresses, an SPI receive buffer and SPI compare  
register.  
Power connections follow conventional descriptions below:  
Connection  
Circuit  
Device  
Power  
Ground  
VCC  
GND  
VDD  
VSS  
1
CP95DZ81301 (8/95)  

Z86E0612PSC 替代型号

型号 品牌 替代类型 描述 数据表
Z86E0612PSG ZILOG

完全替代

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