Datasheet > XRT7295AEIWTR-F

XRT7295AEIWTR-F

更新时间： 2022-09-29 19:40:44

品牌	Logo	应用领域
艾科嘉 - EXAR		/
页数	文件大小	规格书
15页	964K
描述
IC E3 LINE RECEIVER 20SOJ

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XRT7295AEIWTR-F 数据手册

XRT7295AE

Figure 7. Test Set-up for Interference Immunity Requirements

Digital Detection

Parameter

Min.

Typ.

Max.

Unit

Attenuator

-20

-16

In addition to the signal amplitude monitoring of the

analogLOSdetector,thedigitalLOSdetectormonitors

the recovered data 1s density. The RLOS alarm goes

high if 160 +/-32 or more consecutive bits. The alarm

goes low when at least eight 1s occur in a a string of 32

consecutive bits. This hysteresis minimizes RLOS

chattering and guarantees a minimum RLOS pulse

width of 32 clock cycles.

Table5. InterferenceRequirement

Interference Immunity

The XRT7295AE complies with the interference test

detailed in Figure 7 and Table 5. The two data genera-

tors are non-synchronous.

NOTE:

RLOS chatter can still occur. When REQB=1, input signal

levels above the analog LOS threshold can still be low

enough to result in a high but error rate. The resultant data

stream (containing errors) can temporarily activate the

digital LOS detector, ad RLOS chatter can occur. There-

fore, RLOS should not be used as a bit error rate monitor.

RLOS chatter can also occur when RLOL is activated

(high).

In-Circuit Test Capability

When pulled low, the ICT pin forces all digital output

buffers (RCLK, RPDATA, RNDATA, RLOS, RLOL

pins) to be placed in a high output impedance state,

This feature allows in-circuit testing to be done on

neighboring devices without concern for XRT7295AE

bufferdamage.Whenforcedhigh,theICTpindoesnot

affect device operation. An internal pull-up device

(nominally 50 kΩ) is provided on this pin; therefore,

userscanleavethispinopenfornormaloperation.This

is the only pin for which the internal pull-up/pull-down

is provided.

PhaseHits

In response to a 180° phase hit in the input data, the

XRT7295AEreturnstoerror-freeoperationinlessthan

2ms. During the reacquisition time, RLOS may be

temporarilyindicated.

BOARDLAYOUTCONSIDERATIONS

Power Supply Bypassing

Recovered Clock and Data Timing

Table 6 and Figure 9 summarize the timing relation-

ships between the high-speed logic signals RCLK,

RPDATA, and RNDATA. All duty cycle and timing

relationships are referenced to V_DD/2 threshold level.

RPDATA and RNDATA change on the rising edge of

RCLK and are valid during the falling edge of RCLK. A

positive pulse at RIN creates a high level on RPDATA

and a low level on RNDATA. A negative pulse creates

a high level on RNDATA and a low level on RPDATA,

and a received zero produces low levels on both

RPDATA and RNDATA.

Figure 8 illustrates the recommended power supply

bypassing network. A 0.1µF capacitor bypasses the

digital supplies. The analog supply V_DDA is bypassed

by using a 0.1µF capacitor and a shield bead that

removes significant amounts of high-frequency noise

generatedbythesystemandbythedevicelogic.Good

quality, high-frequency (low lead inductance) capaci-

tors should be used. Finally, it is most important that

all ground connections be made to a low-impedance

groundplane.

Rev. 2.0.0

1...7 8 91011 12 13...15

中文翻译

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