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XRT7295AEIWTR-F

更新时间： 2022-09-29 19:40:44

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XRT7295AEIWTR-F 数据手册

XRT7295AE

internally generated jitter is a function of the PLL

bandwidth, which in turn is a function of the input 1s

density. For higher 1s densities, the amount of gener-

atedjitterdecreases.Generatedjitteralsodependson

the quality of the power supply bypassing networks

used. Figure 8 shows the suggested bypassing net-

work, and Table 3 lists the typical generated jitter

performance achievable with this network.

Figure 4. Pulse Mask at the 34.368 Mbit/s Interface

Parameter

Value

Pulse Shape (Nominally Rectangular)

All marks of a valid signal must conform with the mask

(see Figure 4), irrespective of the sign

Pair(s) in Each Direction

One coaxial pair

75Ω Resistive

1.0V

Test Load Impedance

Nominal Peak Voltage of a Mark (Pulse)

Peak Voltage of a Space (No Pulse)

Nominal Pulse Width

0V +/-0.1V

14.55ns

Ratio of the Amplitudes of Positive and Negative Pulses

at the Center of a Pulse Interval

0.95 to 1.05

Ratio of the Widths of Positive and Negative Pulses

at the Nominal Half Amplitude

0.95 to 1.05

Table 2. E3 Pulse Specification at the Transmitter Output Port

Rev. 2.0.0

1...4 5 678 9 10...15

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