Datasheet > XRT71D04

XRT71D04

更新时间： 2024-11-06 21:55:23

品牌	Logo	应用领域
艾科嘉 - EXAR		衰减器
页数	文件大小	规格书
22页	248K
描述
4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER

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XRT71D04 数据手册

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XRT71D04

4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER

APRIL 2001

REV. 1.1.1

• Meets output jitter requirement as specified by

ETSI TBR24

GENERAL DESCRIPTION

The XRT71D04 is a four channel, single chip Jitter At-

tenuator, that meets the Jitter transfer characteristic

requirements specified in the ETSI TBR-24, Bellcore

GR-499 and GR-253 standards.

• Meets the Jitter and Wander specifications

described in T1.105.03b,GR-253 and GR-499 stan-

dards

• Selectable buffer size of 16 and 32 bits

• Jitter attenuator can be disabled

• Available in a 80 pin TQFP package

• Single 3.3V or 5.0V supply.

In addition, the XRT71D04 also meets the Jitter and

Wander specifications described in the ANSI

T1.105.03b 1997, Bellcore GR-253 and GR-499 stan-

dards for Desynchronizing and Pointer adjustments in

the DS3 to STS-SPE mapping applications.

• Operates over - 40⁰C to 85⁰C temperature range.

FEATURES

APPLICATIONS

• Meets the E3/DS3/STS-1 jitter requirements

• No external components required

• E3/DS3 Access Equipment

• STS-SPE to DS3 Mapper

• DSLAMs

• Compliant with jitter transfer template outlined in

ITU G.751, G.752, G.755, GR-499-CORE,1995

GR-253-CORE standards

FIGURE 1. BLOCK DIAGRAM (ONE CHANNEL)

MCLK_n

Timing Control Block /

Phase locked Loop

STS1_n

ICT

DS3/E3_n

DJA_n

RRCLK_n

RRPOS_n

RClk_n

Write Clock

Read Clock

RClkES

RPOS_n

RNEG_n

16/32 Bit FIFO

RRNEG_n

FL_n

FSS

Channel 0

Channel 1

Channel 2

Channel 3

MODE_CTRL

HOST

Reset

Microprocessor Serial

Interface

XRT71D04

n = 0, 1, 2, 3

CS SDI SDO SClk

Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com

12 3 4 5 6 7...22

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