Datasheet > XR81112-F

XR81112-F

更新时间： 2024-11-25 01:13:11

品牌	Logo	应用领域
艾科嘉 - EXAR		时钟外围集成电路晶体
页数	文件大小	规格书
12页	256K
描述
Universal Clock - High Frequency LVCMOS/LVDS/LVPECL Clock Synthesizer

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中文翻译

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技术参数
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XR81112-F 技术参数

生命周期：	Obsolete	包装说明：	QFN-12
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.84
JESD-30 代码：	S-XQCC-N12	长度：	3 mm
端子数量：	12	最高工作温度：	85 °C
最低工作温度：	-40 °C	最大输出时钟频率：	1500 MHz
封装主体材料：	UNSPECIFIED	封装代码：	HVQCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
主时钟/晶体标称频率：	60 MHz	座面最大高度：	1 mm
最大供电电压：	3.465 V	最小供电电压：	3.135 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	宽度：	3 mm
uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER	Base Number Matches：	1

XR81112-F 数据手册

XR81112

Universal Clock - High Frequency

LVCMOS/LVDS/LVPECL Clock Synthesizer

General Description

FEATURES

• Small footprint 3mm x 3mm QFN package

The XR81112 is a family of Universal Clock synthesizer devices in a com-

pact QFN-12 package. The devices generate ANY frequency in the range of

10 MHz to 1.5GHz by utilizing a highly flexible delta sigma modulator and a

wide ranging VCO. The outputs are configurable for single ended LVCMOS

or differential LVDS or LVPECL. The clock outputs have very low phase

noise jitter of sub 0.6ps while consuming extremely low power. These

devices can be used with standard crystals or an external system clock and

can be configured to select from four different frequency multiplier settings to

support a wide variety of applications. This family of products have an

extremely low power PLL block with core power consumption less than 40%

of equivalent devices in the market.

• Configurable - As one differential LVPECL/LVDS

output pair or as a single ended LVCMOS output

• Crystal oscillator interface which can also be

overdriven using a single-ended reference clock

• Output frequency range: 10MHz - 1500MHz

• Crystal/input frequency: 10MHz to 60MHz, paral-

lel resonant crystal

• VCO range: 2GHz - 3GHz

• RMS phase jitter @ 156.25MHz, 12KHz - 20MHz:

<0.60ps

• Full 3.3V or 2.5V operating supply

• -40°C to 85°C ambient operating temperature

• Lead-free (RoHS 6) package

The XR81112 is a clock synthesizer with Integer/fractional divider, LVCMOS/

LVDS/LVPECL driver, 3.3V/2.5V supply, taking a Xtal input and providing

one of four selectable output frequencies. The device is optimized for use

with a fundamental mode 10MHz to 60MHz crystal (or system clock) and

generates a selection of output frequencies from 10MHz to 1.5GHz in either

integer or fractional mode. In fractional mode, frequency resolution of less

than 1Hz steps can be achieved.

APPLICATIONS

• 10GE, GE LAN/WAN

• 2.5G/10G SONET/SDH/OTN

• xDSL, PCIe

The application diagram below shows a typical synthesizer configuration

with any standard crystal oscillating in fundamental mode. Internal load

capacitors are optionally available to minimize/eliminate external crystal

loads. A system clock can also be used to overdrive the oscillator for a syn-

chronous timing system.

• Low-jitter Clock Generation

• Synchronized clock systems

Ordering Information – back page

The typical phase noise plot below shows the jitter integrated over the

12KHz to 20MHz range that is widely used in WAN systems. The typical

noise for the integration range of 1.875MHz to 20MHz is sub 200fs which is

important for LAN applications. These clock devices show a very good high

frequency noise floor below -150dB.

Typical Application

XR81112ꢀPHASEꢀNOISEꢀ(dBc/Hz)ꢀ@ꢀ156.25MHz

XR81112

-40db

-60db

V_CC

2.5Vꢀorꢀ3.3V

RMS Jitter = 542.0fs

XTAL_IN

Int Range 12KHz to 20MHz

10MHzꢀtoꢀ1.5GHz

-80db

10MHzꢀtoꢀ60MHz

-100db

-120db

-140db

-160db

-180db

XTAL_OUT

Enable

FSEL1

FreqꢀSelect

FSEL0

V_EE

100Hz

1KHz

10KHz

100KHz

1MHz

10MHz

1 / 12

exar.com/XR81112

Rev 1A

12 3 4 5 6 7...12

中文翻译

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