XR81411
Universal Quad Clock - High Frequency
LVCMOS/LVDS/LVPECL Clock Synthesizer
General Description
FEATURES
• Small footprint 5mm x 5mm LGA package
• Configurable Outputs - As differential LVPECL/
LVDS pair or as a single ended LVCMOS.
• Crystal oscillator interface which can also be
overdriven using a single-ended reference clock
• Output frequency range: 10MHz - 800MHz
• Crystal/input frequency: 10MHz to 60MHz, paral-
lel resonant crystal
• VCO range: 2GHz - 3GHz
• Phase jitter @
- 125MHz (12KHz - 20MHz): <0.6ps RMS
- 125MHz (1.875MHz -20MHz): <0.25ps RMS
The XR81411 is a Quad Clock synthesizer with 4 independent PLLs in a
compact LGA-45 package. Each synthesizer generates ANY frequency in
the range of 10 MHz to 800MHz by utilizing a highly flexible delta sigma
modulator and a wide ranging VCO. The outputs are independently configu-
rable for single ended LVCMOS or differential LVDS or LVPECL. The clock
outputs have very low typical phase noise jitter of sub 0.6ps RMS, while
consuming extremely low power. The XR81411 uses a single reference and
provides 4 independent outputs that can be configured as needed to sup-
port a wide variety of applications.
Each of the XR81411’s 4 independent PLLs include an integer/fractional
divider, LVCMOS/LVDS/LVPECL output driver, 3.3V/2.5V supply, and gener-
ates one of four selectable output frequencies from a single reference. The
XR81411 is optimized for use with a fundamental mode 10MHz to 60MHz
crystal (or system clock) and generates a selection of output frequencies
ranging from 10MHz to 800MHz in either integer or fractional mode. In frac-
tional mode, frequency resolution of better than 2Hz steps can be achieved.
• 3.3V or 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHS 6) package
APPLICATIONS
• 10GE, GE LAN/WAN
• 2.5G/10G SONET/SDH/OTN
• xDSL, PCIe
• Low-jitter Clock Generation
• Synchronized clock systems
The application diagram below shows a typical LAN synthesizer configura-
tion with any standard crystal oscillating in fundamental mode.
The typical phase noise plot below shows the jitter integrated over the
12KHz to 20MHz range that is widely used in these systems.
Ordering Information – Last Page
Typical Application Diagram and Performance
PHASE NOISE
Qs=125MHz CMOS Output
XR81411
0
Q1=125MHz
Q2=125MHz
Q3=125MHz
Q4=125MHz
Xtal_In
LVCMOS *
(10-200MHz)
Q1
Q1
-20
-40
25MHz
Xtal_Out
LVPECL *
(10-800MHz)
Q2
Q2
-60
-80
LVDS *
(10-800MHz)
Q3
Q3
-100
-120
-140
-160
-180
Control
Pins
LVCMOS *
(10-200MHz)
Q4
Q4
(* Any Frequency, Any Output Format)
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
OFFSET FREQUENCY(Hz)
1 / 15
exar.com/XR81411
Rev 1A
© 2014 Exar Corporation