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XR17V252 PDF预览

XR17V252

更新时间: 2024-11-23 03:53:03
品牌 Logo 应用领域
艾科嘉 - EXAR PC
页数 文件大小 规格书
69页 1498K
描述
66 MHZ PCI BUS DUAL UART WITH POWER MANAGEMENT SUPPORT

XR17V252 数据手册

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XR17V252  
66 MHZ PCI BUS DUAL UART WITH POWER MANAGEMENT SUPPORT  
MARCH 2006  
REV. 1.0.1  
GENERAL DESCRIPTION  
Multi-port RS-232/RS-422/RS-485 Cards  
Point-of-Sale Systems  
FEATURES  
1
The XR17V252 (V252) is a single chip 2-channel  
66MHz PCI UART (Universal Asynchronous Receiver  
and Transmitter) solution, optimized for higher  
performance and lower power. The V252 device with  
its fifth generation register set is designed to meet the  
High performance 32-bit 66MHz PCI UART  
PCI 3.0 compliant  
high  
bandwidth  
and  
power  
management  
PCI power management rev. 1.1 compliant  
EEPROM interface for PCI configuration  
3.3V supply with 5V tolerant non-PCI (serial) inputs  
Data read/write burst operation  
requirements for multi-serial communication ports for  
system administration and management. The 32-bit  
66MHz PCI interface is compliant with PCI 3.0 and  
PCI power management revision 1.1 specifications.  
The device provides an upgrade path for Exar’s  
33MHz 5V and Universal PCI UART family.  
Global interrupt register for both UART channels  
Up to 8 Mbps serial data rate  
The V252 consists of two independent UART  
channels, each with set of configuration and  
enhanced registers, 64 bytes of Transmit (TX) and  
Receive (RX) FIFOs, and a fractional Baud Rate  
Generator (BRG). A global interrupt source register  
provides a complete interrupt status indication for  
both channels to speed up interrupt parsing. The  
V252 device operates at 33/66MHz and features fully  
programmable TX and RX FIFO level triggers,  
automatic hardware and software flow control, and  
automatic RS-485 half duplex direction control output  
for software and hardware design simplification.  
Eight multi-purpose inputs/outputs  
A 16-bit general purpose timer/counter  
Sleep mode with wake-up Indicator  
Two independent UART channels controlled with  
16C550 compatible register Set  
64-byte TX and RX FIFOs with level counters  
and programmable trigger levels  
Fractional baud rate generator  
NOTE 1: Covered by U.S. Patents #5,649,122 and #5,949,787  
Automatic RTS/CTS or DTR/DSR hardware  
flow control with programmable hysteresis  
APPLICATIONS  
Automatic Xon/Xoff software flow control  
Remote Access Servers  
RS-485 half duplex direction control output  
Storage Network Management  
Factory Automation and Process Control  
Instrumentation  
with selectable turn-around delay  
Infrared (IrDA 1.0) data encoder/decoder  
FIGURE 1. BLOCK DIAGRAM OF THE XR17V252  
3.3 V VCC  
(5 V Tolerant  
Serial Inputs)  
CLK( up to  
66 MHz)  
RST#  
UART Channel 0  
AD[31:0]  
64 Byte TX FIFO  
TX0 , RX0 , DTR0#,  
UART  
C/BE[3:0]#  
FRAME#  
Regs  
DSR0 #, RTS0#,  
CTS0 #, CD0 #,RI0#  
IR  
ENDEC  
TX & RX  
PCI Local  
IRDY#  
BRG  
64 Byte RX FIFO  
Device  
Bus  
TRDY#  
Configuration  
Interface  
DEVSEL#  
Registers  
UART Channel 1  
STOP#  
INTA#  
IDSEL  
PERR#  
SERR#  
TX1 , RX1 , DTR1#,  
64 Byte TX FIFO  
UART  
Regs  
DSR1 #, RTS1#,  
CTS1 #, CD1 #,RI1#  
IR  
TX & RX  
ENDEC  
BRG  
64 Byte RX FIFO  
PAR  
Configuration  
PME#  
Space  
Registers  
16-bit  
Timer/Counter  
Multi-purpose  
EECK  
EEDI  
MPIO0- MPIO7  
EEPROM  
Interface  
Inputs/ Outputs  
EEDO  
EECS  
XTAL1  
XTAL2  
Crystal Osc / Buffer  
ENIR  
EN485#  
TMRCK  
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com  

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